Datasheet LTC3727A-1 (Analog Devices) - 10

LTC3727A-1
OPERATION (Refer to Functional Diagram) Main Control Loop Low Current Operation
The LTC3727A-1 uses a constant frequency, current The FCB pin is a multifunction pin providing two func- mode step-down architecture with the two controller tions: 1) to provide regulation for a secondary winding channels operating 180 degrees out of phase. During by temporarily forcing continuous PWM operation on normal operation, each top MOSFET is turned on when both controllers; and 2) to select between two modes of the clock for that channel sets the RS latch, and turned low current operation. When the FCB pin voltage is below off when the main current comparator, I1, resets the RS 0.8V, the controller forces continuous PWM current mode latch. The peak inductor current at which I1 resets the RS operation. In this mode, the top and bottom MOSFETs are latch is controlled by the voltage on the ITH pin, which is alternately turned on to maintain the output voltage inde- the output of each error amplifi er EA. The VOSENSE pin pendent of direction of inductor current. When the FCB pin receives the voltage feedback signal, which is compared is below VINTVCC – 2V but greater than 0.8V, the controller to the internal reference voltage by the EA. When the load enters Burst Mode operation. Burst Mode operation sets current increases, it causes a slight decrease in VOSENSE a minimum output current level before inhibiting the top relative to the 0.8V reference, which in turn causes the switch and turns off the synchronous MOSFET(s) when ITH voltage to increase until the average inductor current the inductor current goes negative. This combination of matches the new load current. After the top MOSFET has requirements will, at low currents, force the ITH pin below turned off, the bottom MOSFET is turned on until either the a voltage threshold that will temporarily inhibit turn-on of inductor current starts to reverse, as indicated by current both output MOSFETs until the output voltage drops. There comparator I2, or the beginning of the next cycle. is 60mV of hysteresis in the burst comparator B tied to the I The top MOSFET drivers are biased from fl oating bootstrap TH pin. This hysteresis produces output signals to the MOSFETs that turn them on for several cycles, followed by capacitor CB, which normally is recharged during each off a variable “sleep” interval depending upon the load cur- cycle through an external diode when the top MOSFET rent. The resultant output voltage ripple is held to a very turns off. As VIN decreases to a voltage close to VOUT, small value by having the hysteretic comparator follow the loop may enter dropout and attempt to turn on the the error amplifi er gain block. top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 400ns every
Frequency Synchronization
tenth cycle to allow CB to recharge. The phase-locked loop allows the internal oscillator to The main control loop is shut down by pulling the be synchronized to an external source via the PLLIN pin. RUN/SS pin low. Releasing RUN/SS allows an internal The output of the phase detector at the PLLFLTR pin is 1.2μA current source to charge soft-start capacitor CSS. also the DC frequency control input of the oscillator that When CSS reaches 1.5V, the main control loop is enabled operates over a 250kHz to 550kHz range corresponding with the ITH voltage clamped at approximately 30% of its to a DC voltage input from 0V to 2.4V. When locked, the maximum value. As CSS continues to charge, the ITH pin PLL aligns the turn on of the top MOSFET to the rising voltage is gradually released allowing normal, full-current edge of the synchronizing signal. When PLLIN is left operation. When both RUN/SS1 and RUN/SS2 are low, all open, the PLLFLTR pin goes low, forcing the oscillator to LTC3727A-1 controller functions are shut down, including its minimum frequency. the 7.5V and 3.3V regulators. 3727a1fa 10