Datasheet LTC3736 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | Dual 2-Phase, No RSENSE , Synchronous Controller with Output Tracking |
| 页数 / 页 | 28 / 7 — PI FU CTIO S (UF/GN Package). SW1/SW2 (Pins 22, 10/Pins 1, 13):. … |
| 文件格式/大小 | PDF / 447 Kb |
| 文件语言 | 英语 |
PI FU CTIO S (UF/GN Package). SW1/SW2 (Pins 22, 10/Pins 1, 13):. IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5):
该数据表的模型线
文件文字版本
LTC3736
U U U PI FU CTIO S (UF/GN Package)
For auxiliary winding applications, connect to a resistor
SW1/SW2 (Pins 22, 10/Pins 1, 13):
Switch Node Connec- divider from the auxiliary output. To synchronize with an tion to Inductor. Also the negative input to differential peak external clock using the PLL, apply a CMOS compatible current comparator and an input to the reverse current clock with a frequency between 250kHz and 850kHz. To comparator. Normally connected to the drain of the exter- select Burst Mode operation at light loads, tie this pin to VIN. nal P-channel MOSFETs, the drain of the external N-channel Grounding this pin selects forced continuous operation, MOSFET and the inductor. which allows the inductor current to reverse. When
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5):
Three-State Pins to synchronized to an external clock, pulse-skipping operation Select Maximum Peak Sense Voltage Threshold. These pins is enabled at light loads. select the maximum allowed voltage drop between the
BG1/BG2 (Pins 19, 13/Pins 22, 16):
Bottom (NMOS) Gate SENSE+ and SW pins (i.e., the maximum allowed drop Drive Output. These pins drive the gates of the external N- across the external P-channel MOSFET) for each channel. channel MOSFETs. These pins have an output swing from Tie to VIN, GND or float to select 204mV, 85mV or 125mV PGND to SENSE+. respectively.
SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14):
Positive
VFB1/VFB2 (Pins 24, 7/Pins 3, 10):
Feedback Pins. Receives Input to Differential Current Comparator. Also powers the the remotely sensed feedback voltage for its controller from gate drivers. Normally connected to the source of the ex- an external resistor divider across the output. ternal P-channel MOSFET.
U U W FU CTIO AL DIAGRA (Common Circuitry)
RVIN VIN (TO CONTROLLER 1, 2) VIN CVIN UNDERVOLTAGE VOLTAGE 0.6V LOCKOUT REFERENCE VREF 0.7µA SHDN RUN/SS tSEC = 1ms + EXTSS INTSS – SYNC/FCB BURSTDIS BURST DEFEAT/ SYNC DETECT PHASE DETECTOR PLLLPF CLK1 VOLTAGE SLOPE1 SLOPE CONTROLLED CLK2 COMP OSCILLATOR SLOPE2 – – VFB1 UV1 FCB FCB PGOOD OV1 + + 0.6V SHDN 0.54V IPRG1 VOLTAGE IPROG1 MAXIMUM + CONTROLLED OV2 3736 FD IPRG2 SENSE VOLTAGE UV2 OSCILLATOR SELECT IPROG2 VFB2 – 3736fa 7
U U U PI FU CTIO S (UF/GN Package)
For auxiliary winding applications, connect to a resistor
SW1/SW2 (Pins 22, 10/Pins 1, 13):
Switch Node Connec- divider from the auxiliary output. To synchronize with an tion to Inductor. Also the negative input to differential peak external clock using the PLL, apply a CMOS compatible current comparator and an input to the reverse current clock with a frequency between 250kHz and 850kHz. To comparator. Normally connected to the drain of the exter- select Burst Mode operation at light loads, tie this pin to VIN. nal P-channel MOSFETs, the drain of the external N-channel Grounding this pin selects forced continuous operation, MOSFET and the inductor. which allows the inductor current to reverse. When
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5):
Three-State Pins to synchronized to an external clock, pulse-skipping operation Select Maximum Peak Sense Voltage Threshold. These pins is enabled at light loads. select the maximum allowed voltage drop between the
BG1/BG2 (Pins 19, 13/Pins 22, 16):
Bottom (NMOS) Gate SENSE+ and SW pins (i.e., the maximum allowed drop Drive Output. These pins drive the gates of the external N- across the external P-channel MOSFET) for each channel. channel MOSFETs. These pins have an output swing from Tie to VIN, GND or float to select 204mV, 85mV or 125mV PGND to SENSE+. respectively.
SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14):
Positive
VFB1/VFB2 (Pins 24, 7/Pins 3, 10):
Feedback Pins. Receives Input to Differential Current Comparator. Also powers the the remotely sensed feedback voltage for its controller from gate drivers. Normally connected to the source of the ex- an external resistor divider across the output. ternal P-channel MOSFET.
U U W FU CTIO AL DIAGRA (Common Circuitry)
RVIN VIN (TO CONTROLLER 1, 2) VIN CVIN UNDERVOLTAGE VOLTAGE 0.6V LOCKOUT REFERENCE VREF 0.7µA SHDN RUN/SS tSEC = 1ms + EXTSS INTSS – SYNC/FCB BURSTDIS BURST DEFEAT/ SYNC DETECT PHASE DETECTOR PLLLPF CLK1 VOLTAGE SLOPE1 SLOPE CONTROLLED CLK2 COMP OSCILLATOR SLOPE2 – – VFB1 UV1 FCB FCB PGOOD OV1 + + 0.6V SHDN 0.54V IPRG1 VOLTAGE IPROG1 MAXIMUM + CONTROLLED OV2 3736 FD IPRG2 SENSE VOLTAGE UV2 OSCILLATOR SELECT IPROG2 VFB2 – 3736fa 7