Datasheet LTC3707-SYNC (Analog Devices) - 8

LTC3707-SYNC
PIN FUNCTIONS RUN/SS1, RUN/SS2 (Pins 1, 15):
Combination of
3.3VOUT (Pin 10):
Output of a linear regulator capable of soft-start, run control inputs and short-circuit detection supplying 10mA DC with peak currents as high as 50mA. timers. A capacitor to ground at each of these pins sets the
PGND (Pin 20):
Driver Power Ground. Connects to the ramp time to full output current. Forcing either of these pins sources of bottom (synchronous) N-channel MOSFETs, back below 1.0V causes the IC to shut down the circuitry anodes of the Schottky rectifi ers and the (–) terminal(s) required for that particular controller. Latchoff overcurrent of C protection is also invoked via this pin as described in the IN. Applications Information section.
INTVCC (Pin 21):
Output of the Internal 5V Linear Low Dropout Regulator and the EXTV
SENSE1+, SENSE2+ (Pins 2, 14):
The (+) Input to the CC Switch. The driver and control circuits are powered from this voltage source. Differential Current Comparators. The ITH pin voltage and Must be decoupled to power ground with a minimum of controlled offsets between the SENSE– and SENSE+ pins in 4.7μF tantalum or other low ESR capacitor. conjunction with RSENSE set the current trip threshold.
EXTV SENSE1–, SENSE2– (Pins 3, 13):
The (–) Input to the
CC (Pin 22):
External Power Input to an Internal Switch Connected to INTV Differential Current Comparators. CC. This switch closes and supplies VCC power, bypassing the internal low dropout regulator, when-
VOSENSE1, VOSENSE2 (Pins 4, 12):
Receives the remotely- ever EXTVCC is higher than 4.7V. See EXTVCC connection sensed feedback voltage for each controller from an external in Applications section. Do not exceed 7V on this pin. resistive divider across the output.
BG1, BG2 (Pins 23, 19):
High Current Gate Drives for
PLLFLTR (Pin 5):
The Phase-Locked Loop’s Lowpass Filter Bottom (Synchronous) N-Channel MOSFETs. Voltage is Tied to This Pin. Alternatively, this pin can be driven swing at these pins is from ground to INTVCC. with an AC or DC voltage source to vary the frequency of
V
the internal oscillator.
IN (Pin 24):
Main Supply Pin. A bypass capacitor should be tied between this pin and the signal ground pin.
PLLIN (Pin 6):
External Synchronization Input to Phase
BOOST1, BOOST2 (Pins 25, 18):
Bootstrapped Supplies Detector. This pin is internally terminated to SGND with to the Top Side Floating Drivers. Capacitors are connected 50kΩ. The phase-locked loop will force the rising top gate between the boost and switch pins and Schottky diodes are signal of controller 1 to be synchronized with the rising tied between the boost and INTV edge of the PLLIN signal. CC pins. Voltage swing at the boost pins is from INTVCC to (VIN + INTVCC).
FCB (Pin 7):
Forced Continuous Control Input. This input
SW1, SW2 (Pins 26, 17):
Switch Node Connections to acts on both controllers and is normally used to regulate Inductors. Voltage swing at these pins is from a Schottky a secondary winding. Pulling this pin below 0.8V will diode (external) voltage drop below ground to V force continuous synchronous operation. Do not leave IN. this pin fl oating.
TG1, TG2 (Pins 27, 16):
High Current Gate Drives for Top N-Channel MOSFETs. These are the outputs of fl oating
ITH1, ITH2 (Pins 8, 11):
Error Amplifi er Output and Switching drivers with a voltage swing equal to INTV Regulator Compensation Point. Each associated channels’ CC – 0.5V superimposed on the switch node voltage SW. current comparator trip point increases with this control voltage.
PGOOD (Pin 28):
Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on either V
SGND (Pin 9):
Small Signal Ground common to both OSENSE pin is not within ±7.5% of its set point. controllers, must be routed separately from high current grounds to the common (–) terminals of the COUT capacitors. 3707sfa 8