Datasheet LTC1874 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Dual Constant Frequency Current Mode Step-Down DC/DC Controller |
| 页数 / 页 | 12 / 10 — APPLICATIO S I FOR ATIO. Low Supply Operation. Setting Output Voltage. … |
| 文件格式/大小 | PDF / 190 Kb |
| 文件语言 | 英语 |
APPLICATIO S I FOR ATIO. Low Supply Operation. Setting Output Voltage. Figure 3. Line Regulation of VREF and VITH
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LTC1874
U U W U APPLICATIO S I FOR ATIO
105
Low Supply Operation
VREF Although the controller can function down to approxi- 100 mately 2.0V, the maximum allowable output current is 95 VITH reduced when VIN decreases below 3V. Figure 3 shows the amount of change as the supply is reduced down to 2V. 90 Also shown in Figure 3 is the effect of VIN on VREF as VIN 85 goes below 2.3V. NORMALIZED VOLTAGE (%) 80
Setting Output Voltage
752.0 2.2 2.4 2.6 2.8 3.0 The controller develops a 0.8V reference voltage between INPUT VOLTAGE (V) the feedback (VFB) terminal and ground (see Figure 4). By 1874 F03 selecting resistor R1, a constant current is caused to flow through R1 and R2 to set the overall output voltage. The
Figure 3. Line Regulation of VREF and VITH
regulated output voltage is determined by: R2 V 0. V OUT = 8 1 + R1 VOUT 1/2 LTC1874 R2 4 For most applications, an 80k resistor is suggested for R1. VFB1 To prevent stray pickup, locate resistors R1 and R2 close R1 3 to the LTC1874. GND1 1874F04
Foldback Current Limiting Figure 4. Setting Output Voltage
As described in the Output Diode Selection, the worst- case dissipation occurs with a short-circuited output when the diode conducts the current limit value almost continuously. To prevent excessive heating in the diode, 1/2 LTC1874 foldback current limiting can be added to reduce the VOUT current in proportion to the severity of the fault. R2 13 4 + I V TH/RUN1 FB1 DFB1 Foldback current limiting is implemented by adding di- R1 odes D 3 DFB2 FB1 and DFB2 between the output and the ITH/RUN GND1 pin as shown in Figure 5. In a hard short (VOUT = 0V), the 1874 F05 current will be reduced to approximately 50% of the maximum output current.
Figure 5. Foldback Current Limiting
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U U W U APPLICATIO S I FOR ATIO
105
Low Supply Operation
VREF Although the controller can function down to approxi- 100 mately 2.0V, the maximum allowable output current is 95 VITH reduced when VIN decreases below 3V. Figure 3 shows the amount of change as the supply is reduced down to 2V. 90 Also shown in Figure 3 is the effect of VIN on VREF as VIN 85 goes below 2.3V. NORMALIZED VOLTAGE (%) 80
Setting Output Voltage
752.0 2.2 2.4 2.6 2.8 3.0 The controller develops a 0.8V reference voltage between INPUT VOLTAGE (V) the feedback (VFB) terminal and ground (see Figure 4). By 1874 F03 selecting resistor R1, a constant current is caused to flow through R1 and R2 to set the overall output voltage. The
Figure 3. Line Regulation of VREF and VITH
regulated output voltage is determined by: R2 V 0. V OUT = 8 1 + R1 VOUT 1/2 LTC1874 R2 4 For most applications, an 80k resistor is suggested for R1. VFB1 To prevent stray pickup, locate resistors R1 and R2 close R1 3 to the LTC1874. GND1 1874F04
Foldback Current Limiting Figure 4. Setting Output Voltage
As described in the Output Diode Selection, the worst- case dissipation occurs with a short-circuited output when the diode conducts the current limit value almost continuously. To prevent excessive heating in the diode, 1/2 LTC1874 foldback current limiting can be added to reduce the VOUT current in proportion to the severity of the fault. R2 13 4 + I V TH/RUN1 FB1 DFB1 Foldback current limiting is implemented by adding di- R1 odes D 3 DFB2 FB1 and DFB2 between the output and the ITH/RUN GND1 pin as shown in Figure 5. In a hard short (VOUT = 0V), the 1874 F05 current will be reduced to approximately 50% of the maximum output current.
Figure 5. Foldback Current Limiting
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