Datasheet ADSP-BF606, ADSP-BF607, ADSP-BF608, ADSP-BF609 (Analog Devices) - 4

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADDRESS ARITHMETIC UNIT SP I3 L3 B3 M3 FP I2 L2 B2 M2 P5 I1 L1 B1 M1 DAG1 P4 I0 L0 B0 M0 P3 DAG0 P2 DA1 32 P1 DA0 32 P0 Y 32 32 PREG RAB MEMOR O T SD 32 LD1 32 ASTAT 32 LD0 32 32 SEQUENCER R7.H R7.L R6.H R6.L R5.H R5.L ALIGN 16 16 R4.H R4.L 8 8 8 8 R3.H R3.L DECODE R2.H R2.L R1.H R1.L BARREL R0.H R0.L SHIFTER 40 40 LOOP BUFFER 40 40 A0 A1 CONTROL UNIT 32 32 DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core The 40-bit shifter can perform shifts and rotates and is used to In addition, multiple L1 memory blocks are provided, offering a support normalization, field extract, and field deposit configurable mix of SRAM and cache. The memory manage- instructions. ment unit (MMU) provides memory protection for individual The program sequencer controls the flow of instruction execu- tasks that may be operating on the core and can protect system tion, including instruction alignment and decoding. For registers from unintended access. program flow control, the sequencer supports PC relative and The architecture provides three modes of operation: user mode, indirect conditional jumps (with static branch prediction), and supervisor mode, and emulation mode. User mode has subroutine calls. Hardware supports zero-overhead looping. restricted access to certain system resources, thus providing a The architecture is fully interlocked, meaning that the program- protected software environment, while supervisor mode has mer need not manage the pipeline when executing instructions unrestricted access to the system and core resources. with data dependencies.
INSTRUCTION SET DESCRIPTION
The address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. It contains a multiported The Blackfin processor instruction set has been optimized so register file consisting of four sets of 32-bit index, modify, that 16-bit opcodes represent the most frequently used instruc- length, and base registers (for circular buffering), and eight tions, resulting in excellent compiled code density. Complex additional 32-bit pointer registers (for C-style indexed stack DSP instructions are encoded into 32-bit opcodes, representing manipulation). fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruc- Blackfin processors support a modified Harvard architecture in tion can be issued in parallel with two 16-bit instructions, combination with a hierarchical memory structure. Level 1 (L1) allowing the programmer to use many of the core resources in a memories are those that typically operate at the full processor single instruction cycle. speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The data memory holds data, The Blackfin processor family assembly language instruction set and a dedicated scratchpad data memory stores stack and local employs an algebraic syntax designed for ease of coding and variable information. readability. The instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to Rev. A | Page 4 of 112 | February 2014 Document Outline Blackfin Dual Core Embedded Processor Features Memory Table Of Contents Revision History General Description Blackfin Processor Core Instruction Set Description Processor Infrastructure DMA Controllers CRC Protection Event Handling Trigger Routing Unit (TRU) Pin Interrupts General-Purpose I/O (GPIO) Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Video Subsystem Video Interconnect (VID) Pipelined Vision Processor (PVP) Pixel Compositor (PIXC) Parallel Peripheral Interface (PPI) Processor Safety Features Dual Core Supervision Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Dual Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers 3-Phase PWM Units Link Ports Serial Ports (SPORTs) ACM Interface General-Purpose Counters Serial Peripheral Interface (SPI) Ports UART Ports TWI Controller Interface Removable Storage Interface (RSI) Controller Area Network (CAN) 10/100 Ethernet MAC USB 2.0 On-the-Go Dual-Role Device Controller Power and Clock Management Crystal Oscillator (SYS_XTAL) USB Crystal Oscillator Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit System Debug Unit Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF60x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GP I/O Multiplexing for 349-Ball CSP_BGA ADSP-BF60x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Processor — Absolute Maximum Ratings ESD Sensitivity Processor — Package Information Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read Asynchronous Flash Read Asynchronous Page Mode Read Synchronous Burst Flash Read Asynchronous Write Asynchronous Flash Write All Accesses Bus Request/Bus Grant DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface Timing Link Ports Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing General-Purpose Port Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing CAN Interface Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing RSI Controller Timing 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions Thermal Diode ADSP-BF60x 349-Ball CSP_BGA Ball Assignments 349-Ball CSP_BGA Ball Assignment (Numerical by Ball Number) 349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin Name) 349-Ball CSP_BGA Ball Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide