Datasheet ADSP-BF592 (Analog Devices) - 10

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ADSP-BF592
recommended. The two capacitors and the series resistor shown
“FINE” ADJUSTMENT “COARSE” ADJUSTMENT
in Figure 4 fine tune phase and amplitude of the sine frequency.
REQUIRES PLL SEQUENCING ON-THE-FLY
The capacitor and resistor values shown in Figure 4 are typical values only. The capacitor values are dependent upon the crystal manufacturers’ load capacitance recommendations and the PCB
÷ 1, 2, 4, 8 CCLK
physical layout. The resistor value depends on the drive level
PLL CLKIN
specified by the crystal manufacturer. The user should verify the
5
u
to 64
u
VCO
customized values based on careful investigations on multiple
÷ 1 to 15 SCLK
devices over temperature range.
BLACKFIN SCLK
d
CCLK CLKOUT (SCLK)
Figure 5. Frequency Modification Methods
CLKBUF TO PLL CIRCUITRY
All on-chip peripherals are clocked by the system clock (SCLK).
EN EN
The system clock frequency is programmable by means of the
SELECT
SSEL3–0 bits of the PLL_DIV register. The values programmed
560
⍀ into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15. Table 4 illustrates typical system clock ratios.
EXTCLK CLKIN XTAL 330
⍀
* FOR OVERTONE Table 4. Example System Clock Ratios OPERATION ONLY: Example Frequency Ratios 18 pF * 18 pF * Signal Name Divider Ratio (MHz) SSEL3–0 VCO/SCLK VCO SCLK NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
0010 2:1 100 50
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
0110 6:1 300 50
OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED RESISTOR VALUE SHOULD BE REDUCED TO 0
⍀
.
1010 10:1 400 40 Figure 4. External Crystal Connections Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of f A third-overtone crystal can be used for frequencies above SCLK. The SSEL value can be changed dynamically without any PLL lock latencies by writing 25 MHz. The circuit is then modified to ensure crystal operation the appropriate values to the PLL divisor register (PLL_DIV). only at the third overtone, by adding a tuned inductor circuit as shown in Figure 4. A design procedure for third-overtone oper- The core clock (CCLK) frequency can also be dynamically ation is discussed in detail in (EE-168) Using Third Overtone changed by means of the CSEL1–0 bits of the PLL_DIV register. Crystals with the ADSP-218x DSP on the Analog Devices web- Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in site (www.analog.com)—use site search on “EE-168.” Table 5. This programmable core clock capability is useful for fast core frequency modifications. The Blackfin core runs at a different clock rate than the on-chip peripherals. As shown in Figure 5, the core clock (CCLK) and
Table 5. Core Clock Ratios
system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. An on-chip PLL is capable of multiplying
Example Frequency Ratios
the CLKIN signal by a programmable 5× to 64× multiplication
Signal Name Divider Ratio (MHz)
factor (bounded by specified minimum and maximum VCO
CSEL1–0 VCO/CCLK VCO CCLK
frequencies). The default multiplier is 6×, but it can be modified 00 1:1 300 300 by a software instruction sequence. 01 2:1 300 150 On-the-fly frequency changes can be effected by simply writing to the PLL_DIV register. The maximum allowed CCLK and 10 4:1 400 100 SCLK rates depend on the applied voltages V 11 8:1 200 25 DDINT and VDDEXT; the VCO is always permitted to run up to the frequency speci- fied by the part’s instruction rate. The EXTCLK pin can be The maximum CCLK frequency both depends on the part’s configured to output either the SCLK frequency or the input instruction rate (see Ordering Guide) and depends on the buffered CLKIN frequency, called CLKBUF. When configured applied VDDINT voltage. See Table 8 for details. The maximal sys- to output SCLK (CLKOUT), the EXTCLK pin acts as a refer- tem clock rate (SCLK) depends on the chip package and the ence signal in many timing specifications. While three-stated by applied VDDINT and VDDEXT voltages (see Table 10). default, it can be enabled using the VRCTL register. Rev. B | Page 10 of 44 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory L1 Utility ROM Custom ROM (Optional) I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Watchdog Timer Timers Serial Ports Serial Peripheral Interface (SPI) Ports UART Port Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF592 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 64-Lead LFCSP Lead Assignment Outline Dimensions Automotive Products Ordering Guide