Datasheet ADSP-BF522C, ADSP-BF523C, ADSP-BF524C, ADSP-BF525C, ADSP-BF526C, ADSP-BF527C (Analog Devices) - 5

link to page 5 link to page 5 ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C selected level of attenuation occurs after the initial microphone
50kΩ
signal amplification from the microphone first and second stage gains.
REXT 10kΩ 0dB/20dB/40dB MICIN GAIN BOOST Line and Headphone Outputs
The DAC outputs, the microphone (the sidetone path), and the
AVDD
line inputs (the bypass path) are summed at an output mixer (see Figure 4). This output signal is then applied to both the ste- reo line outputs and stereo headphone outputs.
ADC OR SIDETONE VMID BYPASS LINE INTERNAL CIRCUITRY INPUT AGND
Figure 3. Microphone Input to ADC
SIDETONE MICROPHONE INPUT
The first gain stage is composed of a low noise operational amplifier set to an inverting configuration with integrated
DACSEL
50 kΩ feedback and 10 kΩ input resistors. The default micro- phone input signal gain is 14 dB. An external resistor (R
DAC LINE OUTPUT
EXT) can
OUTPUT AND
be connected in series with the MICIN pin to reduce the first-
HEADPHONE OUTPUT
stage gain of the microphone input signal to as low as 0 dB by
AVDD
using the following equation: Microphone Input Gain = 50 kΩ/(10 kΩ + REXT) The second-stage gain of the microphone signal path is derived
VMID
from the internal microphone boost circuitry. The available set- tings are 0 dB, 20 dB, and 40 dB and are controlled by the MICBOOST (Register R4, Bit D0) and MICBOOST2 (Register
AGND INTERNAL CIRCUITRY
R4, Bit D8) bits. To achieve 20 dB of secondary gain boost, the programmer can select either MICBOOST or MICBOOST2. To Figure 4. Output Signal Chain achieve 40 dB of secondary microphone signal gain, the pro- grammer must select both MICBOOST and MICBOOST2. The codec has a set of efficient headphone amplifier outputs, The MUTEMIC bit (Register R4, Bit D1) mutes the microphone LHPOUT and RHPOUT, that are able to drive 16 Ω or 32 Ω input signal to the ADC. headphones (shown in Figure 5). When using either the line or microphone inputs, the maximum full-scale input to the ADC is 1.0 V rms when AVDD = 3.3 V.
DAC/
Do not apply an input voltage larger than full-scale to avoid
SIDETONE/
overloading the ADC, which causes distortion of sound and
BYPASS
deterioration of audio quality. For best sound quality in both
AVDD
microphone and line inputs, gain should be carefully configured so that the ADC receives a signal equal to its full-scale. This
– RHPOUT
maximizes the signal-to-noise ratio for best total audio quality.
or VMID + LHPOUT Bypass and Sidetone Paths to Output
The line and microphone inputs can be routed and mixed
INTERNAL CIRCUITRY
directly to the output terminals by programming the SIDET-
AGND
ONE (Register R4, Bit D5) and BYPASS (Register R4, Bit D3) registers. In both modes, the analog input signal is routed Figure 5. Headphone Output directly to the output terminals and is not digitally converted. The bypass signal at the output mixer is the same level as the Like the line inputs, the LHPOUT and RHPOUT volumes, by output of the PGA associated with each line input. default, are independently adjusted by setting the LHPVOL The sidetone signal at the output mixer can be attenuated from (Register R2, Bit D0 to Bit D6) and RHPVOL (Register R3, Bit –6 dB to –15 dB in steps of –3 dB by configuring the SIDEATT D0 to Bit D6) bits of the headphone output control registers. (Register R4, Bit D6 and Bit D7) control register bits. The The headphone outputs can be muted by writing codes less than 0110000 to the LHPVOL and RHPVOL bits. Rev. A | Page 5 of 36 | March 2010 Document Outline Blackfin Embedded Processor with Codec Processor Features Embedded Codec Features Peripherals Table of Contents Revision History General Description Codec Description ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Analog Audio Interfaces Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Normal Mode USB Mode Software Control Interface Codec Pin Descriptions Register Details Bit Descriptions Specifications Operating Conditions Codec Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Power Consumption Timing Specifications TWI Timing SPI Timing Digital Audio Interface Slave Mode Timing Digital Audio Interface Master Mode Timing System Clock Timing Digital Filter Characteristics Converter Filter Response Digital De-Emphasis 289-Ball CSP_BGA Ball Assignment Outline Dimensions Ordering Guide