Datasheet ADSP-BF538, ADSP-BF538F (Analog Devices) - 3

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ADSP-BF538/ ADSP-BF538F GENERAL DESCRIPTION
The ADSP-BF538/ADSP-BF538F processors are members of
SYSTEM INTEGRATION
the Blackfin® family of products, incorporating the Analog The ADSP-BF538/ADSP-BF538F processors are highly inte- Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin grated system-on-a-chip solutions for the next generation of processors combine a dual-MAC state-of-the-art signal process- consumer and industrial applications including audio and video ing engine, the advantages of a clean, orthogonal RISC-like signal processing. By combining advanced memory configura- microprocessor instruction set, and single-instruction, multi- tions, such as on-chip flash memory, industry-standard ple-data (SIMD) multimedia capabilities into a single interfaces, and a high performance signal processing core, cost- instruction set architecture. effective solutions can be quickly developed, without the need The ADSP-BF538/ADSP-BF538F processors are completely for costly external components. The system peripherals include code compatible with other Blackfin processors, differing only three UART ports, three SPI ports, four serial ports (SPORTs), with respect to performance, peripherals, and on-chip memory. one CAN interface, two 2-wire interfaces (TWI), four general- Specific performance, peripherals, and memory configurations purpose timers (three with PWM capability), a real-time clock, a are shown in Table 1. watchdog timer, a parallel peripheral interface (PPI), and gen- eral-purpose I/O pins.
Table 1. Processor Features ADSP-BF538/ADSP-BF538F PROCESSOR Feature ADSP-BF538 ADSP-BF538F8 PERIPHERALS
SPORTs 4 4 The ADSP-BF538/ADSP-BF538F processors contain a rich set UARTs 3 3 of peripherals connected to the core via several high bandwidth SPI 3 3 buses, providing flexibility in system configuration as well as excellent overall system performance (see the block diagram 1). TWI 2 2 The general-purpose peripherals include functions such as CAN 1 1 UART, timers with PWM (pulse-width modulation) and pulse PPI 1 1 measurement capability, general-purpose I/O pins, a real-time Internal 8M bit — 1 clock, and a watchdog timer. This set of functions satisfies a Parallel Flash wide variety of typical system support needs and is augmented by the system expansion capabilities of the device. In addition to Instruction 16K bytes 16K bytes these general-purpose peripherals, the processors contain high SRAM/Cache speed serial and parallel ports for interfacing to a variety of Instruction SRAM 64K bytes 64K bytes audio, video, and modem codec functions. A CAN 2.0B control- Data SRAM/Cache 32K bytes 32K bytes ler is provided for automotive and industrial control networks. Data SRAM 32K bytes 32K bytes An interrupt controller manages interrupts from the on-chip peripherals or from external sources. Power management con- Scratchpad 4K bytes 4K bytes trol functions tailor the performance and power characteristics Maximum 533 MHz 533 MHz of the processors and system to many application scenarios. Frequency 1066 MMACS 1066 MMACS All of the peripherals, except for general-purpose I/O, CAN, Package Option BC-316 BC-316 TWI, real-time clock, and timers, are supported by a flexible DMA structure. There are also four separate memory DMA By integrating a rich set of industry-leading system peripherals channels dedicated to data transfers between the processor’s and memory, Blackfin processors are the platform of choice for various memory spaces, including external SDRAM and asyn- next generation applications that require RISC-like program- chronous memory. Multiple on-chip buses running at up to mability, multimedia support, and leading edge signal 133 MHz provide enough bandwidth to keep the processor core processing in one integrated package. running with activity on all of the on-chip and external
LOW POWER ARCHITECTURE
peripherals. The ADSP-BF538/ADSP-BF538F processors include an on-chip Blackfin processors provide world class power management and voltage regulator in support of the processor’s dynamic power performance. They are designed using a low power and low management capability. The voltage regulator provides a range voltage methodology and feature dynamic power management, of core voltage levels from V which is the ability to vary both the voltage and frequency of DDEXT. The voltage regulator can be bypassed as needed. operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life and lower heat dissipation. Rev. E | Page 3 of 60 | November 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF538/ADSP-BF538F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF538F8 Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports General-Purpose Ports Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide