Datasheet ADSP-BF538, ADSP-BF538F (Analog Devices) - 4

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ADSP-BF538/ ADSP-BF538F BLACKFIN PROCESSOR CORE
instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, As shown in Figure 2 on Page 4, the Blackfin processor core and 8-bit subtract/absolute value/accumulate (SAA) operations. contains two 16-bit multipliers, two 40-bit accumulators, two The compare/select and vector search instructions are also 40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu- provided. tation units process 8-bit, 16-bit, or 32-bit data from the register file. For certain instructions, two 16-bit ALU operations can be per- formed simultaneously on register pairs (a 16-bit high half and The compute register file contains eight 32-bit registers. When 16-bit low half of a compute register). Quad 16-bit operations performing compute operations on 16-bit operand data, the are possible using the second ALU. register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported The 40-bit shifter can perform shifts and rotates and is used to register file and instruction constant fields. support normalization, field extract, and field deposit instructions. Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. The program sequencer controls the flow of instruction execu- Signed and unsigned formats, rounding, and saturation are tion, including instruction alignment and decoding. For supported. program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and The ALUs perform a traditional set of arithmetic and logical subroutine calls. Hardware is provided to support zero over- operations on 16-bit or 32-bit data. In addition, many special head looping. The architecture is fully interlocked, meaning that instructions are included to accelerate various signal processing the programmer need not manage the pipeline when executing tasks. These include bit operations such as field extract and pop- instructions with data dependencies. ulation count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video
ADDRESS ARITHMETIC UNIT SP I3 L3 B3 M3 FP I2 L2 B2 M2 P5 I1 L1 B1 M1 DAG1 P4 I0 L0 B0 M0 P3 DAG0 P2 DA1 32 P1 DA0 32 P0 Y 32 32 PREG RAB MEMOR O T SD 32 LD1 32 ASTAT 32 LD0 32 32 SEQUENCER R7.H R7.L R6.H R6.L R5.H R5.L ALIGN 16 16 R4.H R4.L 8 8 8 8 R3.H R3.L DECODE R2.H R2.L R1.H R1.L BARREL R0.H R0.L SHIFTER 40 40 LOOP BUFFER 40 40 A0 A1 CONTROL UNIT 32 32 DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core Rev. E | Page 4 of 60 | November 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF538/ADSP-BF538F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF538F8 Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports General-Purpose Ports Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide