Datasheet ADSP-BF538, ADSP-BF538F (Analog Devices) - 10

ADSP-BF538/ ADSP-BF538F
timer, or as a mechanism for measuring pulse widths and peri- • Interrupts – Each transmit and receive port generates an ods of external events. These timers can be synchronized to an interrupt upon completing the transfer of a data word or external clock input to the PF1 pin (TACLK), an external clock after transferring an entire data buffer or buffers through input to the PPI_CLK pin (TMRCLK), or to the internal SCLK. DMA. The timer units can be used in conjunction with UART0 to • Multichannel capability – Each SPORT supports 128 chan- measure the width of the pulses in the data stream to provide an nels out of a 1024 channel window and is compatible with auto-baud detect function for a serial channel. the H.100, H.110, MVIP-90, and HMVIP standards. The timers can generate interrupts to the processor core provid-
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
ing periodic events for synchronization, either to the system clock or to a count of external signals. The ADSP-BF538/ADSP-BF538F processors incorporate three SPI-compatible ports that enable the processor to communicate In addition to the three general-purpose programmable timers, with multiple SPI compatible devices. a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick The SPI interface uses three pins for transferring data: two data clock for generation of operating system periodic interrupts. pins (master output-slave input, MOSIx, and master input-slave output, MISOx) and a clock pin (serial clock, SCKx). An SPI
SERIAL PORTS (SPORTs)
chip select input pin (SPIxSS) lets other SPI devices select the The ADSP-BF538/ADSP-BF538F processors incorporate four processor. For SPI0, seven SPI chip select output pins (SPI0- dual-channel synchronous serial ports for serial and multipro- SEL7–1) let the processor select other SPI devices. SPI1 and cessor communications. The SPORTs support the following SPI2 each have a single SPI chip select output pin (SPI1SEL1 features: and SPI2SEL1) for SPI point-to-point communication. Each of the SPI select pins are reconfigured GPIO pins. Using these • I2S capable operation. pins, the SPI ports provide a full-duplex, synchronous serial • Bidirectional operation – Each SPORT has two sets of inde- interface, which supports both master/slave modes and multi- pendent transmit and receive pins, enabling 16 channels of master environments. I2S stereo audio. The SPI ports’ baud rate and clock phase/polarities are pro- • Buffered (8-deep) transmit and receive ports – Each port grammable, and they each have an integrated DMA controller, has a data register for transferring data words to and from configurable to support transmit or receive data streams. Each other processor components and shift registers for shifting SPI’s DMA controller can only service unidirectional accesses at data in and out of the data registers. any given time. • Clocking – Each transmit and receive port can either use an The SPI port’s clock rate is calculated as: external serial clock or generate its own, in frequencies ranging from (f f SCLK/131,070) Hz to (fSCLK/2) Hz. SPI Clock Rate SCLK = --------------------- 2  SPIx_BAUD • Word length – Each SPORT supports serial data words from 3 bits to 32 bits in length, transferred most significant where the 16-bit SPIx_BAUD register contains a value of 2 to bit first or least significant bit first. 65,535. • Framing – Each transmit and receive port can run with or During transfers, the SPI port simultaneously transmits and without frame sync signals for each data word. Frame sync receives by serially shifting data in and out on its two serial data signals can be generated internally or externally, active high lines. The serial clock line synchronizes the shifting and sam- or low, and with either of two pulse widths and early or late pling of data on the two serial data lines. frame sync.
2-WIRE INTERFACE
• Companding in hardware – Each SPORT can perform A-law or μ-law companding according to ITU recommen- The ADSP-BF538/ADSP-BF538F processors have two 2-wire dation G.711. Companding can be selected on the transmit interface (TWI) modules that are compatible with the Philips and/or receive channel of the SPORT without additional Inter-IC bus standard. The TWI modules offer the capabilities latencies. of simultaneous master and slave operation, support for 7-bit • DMA operations with single-cycle overhead – Each SPORT addressing and multimedia data arbitration. The TWI also can automatically receive and transmit multiple buffers of includes master clock synchronization and support for clock memory data. The processor can link or chain sequences of low extension. DMA transfers between a SPORT and memory. The TWI interface uses two pins for transferring clock (SCLx) and data (SDAx) and supports the protocol at speeds up to 400 kbps. The TWI interface pins are compatible with 5 V logic levels. Rev. E | Page 10 of 60 | November 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF538/ADSP-BF538F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF538F8 Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports General-Purpose Ports Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide