Datasheet ADSP-BF534, ADSP-BF536, ADSP-BF537 (Analog Devices)

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Blackfin Embedded Processor ADSP-BF534/ADSP-BF536/ADSP-BF537 FEATURES PERIPHERALS Up to 600 MHz high performance Blackfin processor IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, ADSP-BF537 only) 40-bit shifter Controller area network (CAN) 2.0B interface RISC-like register and instruction model for ease of Parallel peripheral interface (PPI), supporting ITU-R 656 programming and compiler-friendly support video data formats Advanced debug, trace, and performance monitoring 2 dual-channel, full-duplex synchronous serial ports Wide range of operating voltages (see Operating Conditions (SPORTs), supporting 8 stereo I2S channels on Page 23) 12 peripheral DMAs, 2 mastered by the Ethernet MAC Qualified for Automotive Applications (see Automotive Prod- 2 memory-to-memory DMAs with external request lines ucts on Page 66 ) Event handler with 32 interrupt inputs Programmable on-chip voltage regulator Serial peripheral interface (SPI) compatible 182-ball and 208-ball CSP_BGA packages 2 UARTs with IrDA support MEMORY 2-wire interface (TWI) controller Eight 32-bit timer/counters with PWM support Up to 132K bytes of on-chip memory Real-time clock (RTC) and watchdog timer Instruction SRAM/cache and instruction SRAM 32-bit core timer Data SRAM/cache plus additional dedicated data SRAM 48 general-purpose I/Os (GPIOs), 8 with high current drivers Scratchpad SRAM (see Table 1 on Page 3 for available On-chip PLL capable of frequency multiplication memory configurations) Debug/JTAG interface External memory controller with glueless support for SDRAM and asynchronous 8-bit and 16-bit memories Flexible booting options from external flash, SPI and TWI memory or from SPI, TWI, and UART host devices Memory management unit providing memory protection VOLTAGE REGULATOR JTAG TEST AND EMULATION PERIPHERAL ACCESS BUS WATCHDOG TIMER RTC INTERRUPT CAN
B
CONTROLLER TWI PORT J SPORT0 L1 L1 DMA INSTRUCTION DATA CONTROLLER SPORT1 MEMORY MEMORY GPIO PORT G PPI S DMA CORE BUS UART0-1 DMA BU EXTERNAL ACCESS BUS EXTERNAL GPIO SPI PORT F EXTERNAL PORT TIMER7-0 FLASH, SDRAM CONTROL ETHERNET MAC GPIO 16 (See Table 1) PORT H BOOT ROM
Figure 1. Functional Block Diagram Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
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Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide