Datasheet ADSP-BF531, ADSP-BF532, ADSP-BF533 (Analog Devices) - 5

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ADSP-BF531/ ADSP-BF532 /ADSP-BF533 ADDRESS ARITHMETIC UNIT SP I3 L3 B3 M3 FP I2 L2 B2 M2 P5 I1 L1 B1 M1 DAG1 P4 I0 L0 B0 M0 DAG0 P3 P2 DA1 32 P1 DA0 32 P0 Y 32 32 RAB PREG MEMOR TO SD 32 LD1 32 ASTAT 32 LD0 32 32 SEQUENCER R7.H R7.L R6.H R6.L R5.H R5.L ALIGN 16 16 R4.H R4.L 8 8 8 8 R3.H R3.L DECODE R2.H R2.L R1.H R1.L BARREL R0.H R0.L SHIFTER 40 40 LOOP BUFFER A0 40 40 A1 CONTROL UNIT 32 32 DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core The second on-chip memory block is the L1 data memory, con- 1M byte segment regardless of the size of the devices used, so sisting of one or two banks of up to 32K bytes. The memory that these banks are only contiguous if each is fully populated banks are configurable, offering both cache and SRAM func- with 1M byte of memory. tionality. This memory block is accessed at full processor speed.
I/O Memory Space
The third memory block is a 4K byte scratchpad SRAM, which runs at the same speed as the L1 memories, but is only accessible Blackfin processors do not define a separate I/O space. All as data SRAM and cannot be configured as cache memory. resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into
External (Off-Chip) Memory
memory mapped registers (MMRs) at addresses near the top of External memory is accessed via the external bus interface unit the 4G byte address space. These are separated into two smaller (EBIU). This 16-bit interface provides a glueless connection to a blocks, one containing the control MMRs for all core functions, bank of synchronous DRAM (SDRAM) as well as up to four and the other containing the registers needed for setup and con- banks of asynchronous memory devices including flash, trol of the on-chip peripherals outside of the core. The MMRs EPROM, ROM, SRAM, and memory mapped I/O devices. are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. The PC133-compliant SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. The SDRAM con-
Booting
troller allows one row to be open for each internal SDRAM The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors con- bank, for up to four internal SDRAM banks, improving overall tain a small boot kernel, which configures the appropriate system performance. peripheral for booting. If the processors are configured to boot The asynchronous memory controller can be programmed to from boot ROM memory space, the processor starts executing control up to four banks of devices with very flexible timing from the on-chip boot ROM. For more information, see Boot- parameters for a wide variety of devices. Each bank occupies a ing Modes on Page 14. Rev. I | Page 5 of 64 | August 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port General-Purpose I/O Port F Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing General-Purpose I/O Port F Pin Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 160-Ball CSP_BGA Ball Assignment 169-Ball PBGA Ball Assignment 176-Lead LQFP Pinout Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide