Datasheet ADSP-BF531, ADSP-BF532, ADSP-BF533 (Analog Devices) - 9

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ADSP-BF531/ ADSP-BF532 /ADSP-BF533
The stopwatch function counts down from a programmed
TIMERS
value, with one second resolution. When the stopwatch is There are four general-purpose programmable timer units in enabled and the counter underflows, an interrupt is generated. the ADSP-BF531/ADSP-BF532/ADSP-BF533 processors. Three Like other peripherals, the RTC can wake up the processor from timers have an external pin that can be configured either as a sleep mode upon generation of any RTC wakeup event. pulse-width modulator (PWM) or timer output, as an input to Additionally, an RTC wakeup event can wake up the processor clock the timer, or as a mechanism for measuring pulse widths from deep sleep mode, and wake up the on-chip internal voltage and periods of external events. These timers can be synchro- regulator from a powered-down state. nized to an external clock input to the PF1 pin (TACLK), an Connect RTC pins RTXI and RTXO with external components external clock input to the PPI_CLK pin (TMRCLK), or to the as shown in Figure 6. internal SCLK. The timer units can be used in conjunction with the UART to
RTXI RTXO
measure the width of the pulses in the data stream to provide an autobaud detect function for a serial channel.
R1
The timers can generate interrupts to the processor core provid- ing periodic events for synchronization, either to the system
X1
clock or to a count of external signals.
C1 C2
In addition to the three general-purpose programmable timers, a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts.
SUGGESTED COMPONENTS: X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR SERIAL PORTS (SPORTs) EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE) C1 = 22 pF
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors
C2 = 22 pF R1 = 10 M
: incorporate two dual-channel synchronous serial ports
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
(SPORT0 and SPORT1) for serial and multiprocessor commu-
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
nications. The SPORTs support the following features: • I2S capable operation. Figure 6. External Components for RTC • Bidirectional operation – Each SPORT has two sets of inde-
WATCHDOG TIMER
pendent transmit and receive pins, enabling eight channels of I2S stereo audio. The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors include a 32-bit timer that can be used to implement a software • Buffered (8-deep) transmit and receive ports – Each port watchdog function. A software watchdog can improve system has a data register for transferring data words to and from availability by forcing the processor to a known state through other processor components and shift registers for shifting generation of a hardware reset, nonmaskable interrupt (NMI), data in and out of the data registers. or general-purpose interrupt, if the timer expires before being • Clocking – Each transmit and receive port can either use an reset by software. The programmer initializes the count value of external serial clock or generate its own, in frequencies the timer, enables the appropriate interrupt, then enables the ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz. timer. Thereafter, the software must reload the counter before it • Word length – Each SPORT supports serial data words counts to zero from the programmed value. This protects the from 3 bits to 32 bits in length, transferred most-signifi- system from remaining in an unknown state where software, cant-bit first or least-significant-bit first. which would normally reset the timer, has stopped running due to an external noise condition or software error. • Framing – Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync If configured to generate a hardware reset, the watchdog timer signals can be generated internally or externally, active high resets both the core and the processor peripherals. After a reset, or low, and with either of two pulse widths and early or late software can determine if the watchdog was the source of the frame sync. hardware reset by interrogating a status bit in the watchdog timer control register. • Companding in hardware – Each SPORT can perform A-law or μ-law companding according to ITU recommen- The timer is clocked by the system clock (SCLK), at a maximum dation G.711. Companding can be selected on the transmit frequency of fSCLK. and/or receive channel of the SPORT without additional latencies. • DMA operations with single-cycle overhead – Each SPORT can automatically receive and transmit multiple buffers of memory data. The processor can link or chain sequences of DMA transfers between a SPORT and memory. Rev. I | Page 9 of 64 | August 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port General-Purpose I/O Port F Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing General-Purpose I/O Port F Pin Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 160-Ball CSP_BGA Ball Assignment 169-Ball PBGA Ball Assignment 176-Lead LQFP Pinout Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide