Datasheet ADSP-BF561 (Analog Devices) - 5

ADSP-BF561
CORE A MEMORY MAP CORE B MEMORY MAP 0xFFFF FFFF CORE MMR REGISTERS CORE MMR REGISTERS 0xFFE0 0000 0xFFC0 0000 SYSTEM MMR REGISTERS RESERVED 0xFFB0 1000 L1 SCRATCHPAD SRAM (4K) 0xFFB0 0000 RESERVED 0xFFA1 4000 L1 INSTRUCTION SRAM/CACHE (16K) 0xFFA1 0000 RESERVED 0xFFA0 4000 L1 INSTRUCTION SRAM (16K) 0xFFA0 0000 RESERVED RESERVED 0xFF90 8000 L1 DATA BANK B SRAM/CACHE (16K) 0xFF90 4000 L1 DATA BANK B SRAM (16K) 0xFF90 0000 RESERVED 0xFF80 8000 L1 DATA BANK A SRAM/CACHE (16K) 0xFF80 4000 L1 DATA BANK A SRAM (16K) 0xFF80 0000 0xFF80 0000 RESERVED 0xFF70 1000 INTERNAL MEMORY L1 SCRATCHPAD SRAM (4K) 0xFF70 0000 RESERVED 0xFF61 4000 L1 INSTRUCTION SRAM/CACHE (16K) 0xFF61 0000 RESERVED 0xFF60 4000 L1 INSTRUCTION SRAM (16K) RESERVED 0xFF60 0000 RESERVED 0xFF50 8000 L1 DATA BANK B SRAM/CACHE (16K) 0xFF50 4000 L1 DATA BANK B SRAM (16K) 0xFF50 0000 RESERVED 0xFF40 8000 L1 DATA BANK A SRAM/CACHE (16K) 0xFF40 4000 L1 DATA BANK A SRAM (16K) 0xFF40 0000 RESERVED 0xFEB2 0000 L2 SRAM (128K) 0xFEB0 0000 RESERVED 0xEF00 4000 BOOT ROM 0xEF00 0000 RESERVED 0x3000 0000 ASYNC MEMORY BANK 3 0x2C00 0000 ASYNC MEMORY BANK 2 0x2800 0000 ASYNC MEMORY BANK 1 0x2400 0000 ASYNC MEMORY BANK 0 0x2000 0000 RESERVED EXTERNAL MEMORY Top of last SDRAM page SDRAM BANK 3 SDRAM BANK 2 SDRAM BANK 1 SDRAM BANK 0 0x0000 0000
Figure 3. Memory Map The fourth on-chip memory system is the L2 SRAM memory
External (Off-Chip) Memory
array which provides 128K bytes of high speed SRAM operating The ADSP-BF561 external memory is accessed via the External at one half the frequency of the core, and slightly longer latency Bus Interface Unit (EBIU). This interface provides a glueless than the L1 memory banks. The L2 memory is a unified instruc­ connection to up to four banks of synchronous DRAM tion and data memory and can hold any mixture of code and (SDRAM) as well as up to four banks of asynchronous memory data required by the system design. The Blackfin cores share a devices, including flash, EPROM, ROM, SRAM, and memory dedicated low latency 64-bit wide data path port into the L2 mapped I/O devices. SRAM memory. The PC133-compliant SDRAM controller can be programmed Each Blackfin core processor has its own set of core Memory to interface to up to four banks of SDRAM, with each bank con­ Mapped Registers (MMRs) but share the same system MMR taining between 16M bytes and 128M bytes providing access to registers and 128K bytes L2 SRAM memory. up to 512M bytes of SDRAM. Each bank is independently pro­ grammable and is contiguous with adjacent banks regardless of the sizes of the different banks or their placement. This allows Rev. E | Page 5 of 64 | September 2009 Document Outline Features Peripherals Table of Contents Revision History General Description Portable Low Power Architecture Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port Programmable Flags (PFx) Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode-Maximum Performance Active Operating Mode-Moderate Power Savings Sleep Operating Mode-High Dynamic Power Savings Deep Sleep Operating Mode-Maximum Dynamic Power Savings Hibernate State-Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools EZ-KIT Lite Evaluation Board Designing an Emulator-Compatible Processor Board Related Documents Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port- Master Timing Serial Peripheral Interface (SPI) Port- Slave Timing Universal Asynchronous Receiver Transmitter (UART) Port-Receive and Transmit Timing Programmable Flags Cycle Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Power Dissipation Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 256-Ball CSP_BGA (17 mm) Ball Assignment 256-Ball CSP_BGA (12 mm) Ball Assignment 297-Ball PBGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide