Datasheet ADSP-BF561 (Analog Devices) - 10

link to page 17 ADSP-BF561 • PIO (programmed I/O) – The processor sends or receives • Flag interrupt mask registers – These registers allow each data by writing or reading I/O-mapped UART registers. individual PFx pin to function as an interrupt to the pro­ The data is double-buffered on both transmit and receive. cessor. Similar to the flag control registers that are used to • DMA (direct memory access) – The DMA controller trans­ set and clear individual flag values, one flag interrupt mask fers both transmit and receive data. This reduces the register sets bits to enable an interrupt function, and the number and frequency of interrupts required to transfer other flag interrupt mask register clears bits to disable an data to and from memory. The UART has two dedicated interrupt function. PFx pins defined as inputs can be con­ DMA channels, one for transmit and one for receive. These figured to generate hardware interrupts, while output PFx DMA channels have lower default priority than most DMA pins can be configured to generate software interrupts. channels because of their relatively low service rates. • Flag interrupt sensitivity registers – These registers specify The baud rate, serial data format, error code generation and whether individual PFx pins are level- or edge-sensitive status, and interrupts for the UART port are programmable. and specify, if edge-sensitive, whether just the rising edge or both the rising and falling edges of the signal are signifi­ The UART programmable features include: cant. One register selects the type of sensitivity, and one • Supporting bit rates ranging from (f /1,048,576) bits per register selects which edges are significant for edge SCLK second to (f /16) bits per second. sensitivity. SCLK • Supporting data formats from seven bits to 12 bits per
PARALLEL PERIPHERAL INTERFACE
frame. The ADSP-BF561 processor provides two parallel peripheral • Both transmit and receive operations can be configured to interfaces (PPI0, PPI1) that can connect directly to parallel A/D generate maskable interrupts to the processor. and D/A converters, video encoders and decoders, and other The UART port’s clock rate is calculated as: general-purpose peripherals. The PPI consists of a dedicated f input clock pin, up to 3 frame synchronization pins, and up to SCLK UART Clock Rate = ------------------------ 16 × UART_Divisor 16 data pins. The input clock supports parallel data rates at up to f /2 MHz, and the synchronization signals can be configured SCLK Where the 16-bit UART_Divisor comes from the UART_DLH as either inputs or outputs. register (most significant 8 bits) and UART_DLL register (least significant 8 bits). The PPI supports a variety of general-purpose and ITU-R 656 modes of operation. In general-purpose mode, the PPI provides In conjunction with the general-purpose timer functions, half-duplex, bi-directional data transfer with up to 16 bits of autobaud detection is supported. data. Up to 3 frame synchronization signals are also provided. The capabilities of the UART are further extended with support In ITU-R 656 mode, the PPI provides half-duplex, bi-direc­ for the Infrared Data Association (IrDA®) serial infrared physi­ tional transfer of 8- or 10-bit video data. Additionally, on-chip cal layer link specification (SIR) protocol. decode of embedded start-of-line (SOL) and start-of-field (SOF) preamble packets is supported.
PROGRAMMABLE FLAGS (PFx) General-Purpose Mode Descriptions
The ADSP-BF561 has 48 bidirectional, general-purpose I/O, programmable flag (PF47–0) pins. Some programmable flag The general-purpose modes of the PPI are intended to suit a pins are used by peripherals (see Pin Descriptions on Page 17). wide variety of data capture and transmission applications. When not used as a peripheral pin, each programmable flag can Three distinct submodes are supported: be individually controlled by manipulation of the flag control, • Input mode – frame syncs and data are inputs into the PPI. status, and interrupt registers as follows: • Frame capture mode – frame syncs are outputs from the • Flag direction control register – Specifies the direction of PPI, but data are inputs. each individual PFx pin as input or output. • Output mode – frame syncs and data are outputs from the • Flag control and status registers – Rather than forcing the PPI. software to use a read-modify-write process to control the setting of individual flags, the ADSP-BF561 employs a
Input Mode
“write one to set” and “write one to clear” mechanism that Input mode is intended for ADC applications, as well as video allows any combination of individual flags to be set or communication with hardware signaling. In its simplest form, cleared in a single instruction, without affecting the level of PPI_FS1 is an external frame sync input that controls when to any other flags. Two control registers are provided, one read data. The PPI_DELAY MMR allows for a delay (in register is written-to in order to set flag values, while PPI_CLK cycles) between reception of this frame sync and the another register is written-to in order to clear flag values. initiation of data reads. The number of input data samples is Reading the flag status register allows software to interro­ user programmable and defined by the contents of the gate the sense of the flags. PPI_COUNT register. The PPI supports 8-bit, and 10-bit through 16-bit data, and are programmable in the PPI_CONTROL register. Rev. E | Page 10 of 64 | September 2009 Document Outline Features Peripherals Table of Contents Revision History General Description Portable Low Power Architecture Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port Programmable Flags (PFx) Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode-Maximum Performance Active Operating Mode-Moderate Power Savings Sleep Operating Mode-High Dynamic Power Savings Deep Sleep Operating Mode-Maximum Dynamic Power Savings Hibernate State-Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools EZ-KIT Lite Evaluation Board Designing an Emulator-Compatible Processor Board Related Documents Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port- Master Timing Serial Peripheral Interface (SPI) Port- Slave Timing Universal Asynchronous Receiver Transmitter (UART) Port-Receive and Transmit Timing Programmable Flags Cycle Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Power Dissipation Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 256-Ball CSP_BGA (17 mm) Ball Assignment 256-Ball CSP_BGA (12 mm) Ball Assignment 297-Ball PBGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide