Datasheet ADAU1401A (Analog Devices) - 6

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ADAU1401A POWER Table 4. Parameter Min Typ Max1 Unit
SUPPLY VOLTAGE Analog Voltage 3.3 V Digital Voltage 1.8 V PLL Voltage 3.3 V IOVDD Voltage 3.3 V SUPPLY CURRENT Analog Current (AVDD and PVDD) 50 85 mA Digital Current (DVDD) 25 40 mA Analog Current, Reset 35 55 mA Digital Current, Reset 1.5 4.5 mA DISSIPATION Operation (AVDD, DVDD, PVDD)2 259.5 mW Reset, All Supplies 118 mW POWER SUPPLY REJECTION RATIO (PSRR) 1 kHz, 200 mV p-p Signal at AVDD 50 dB 1 Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V. 2 Power dissipation does not include IOVDD power because the current drawn from this supply is dependent on the loads at the digital output pins.
TEMPERATURE RANGE Table 5. Parameter Min Typ Max Unit
Functionality Guaranteed −40 +105 °C ambient
PLL AND OSCILLATOR Table 6. Parameter
1
Min Typ Max Unit
PLL Operating Range MCLK_Nom − 20% MCLK_Nom + 20% MHz PLL Lock Time 20 ms Crystal Oscillator Transconductance (gm) 78 mmho 1 Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
REGULATOR Table 7. Parameter
1
Min Typ Max Unit
DVDD Voltage 1.7 1.8 1.84 V 1 Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit. Rev. A | Page 6 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER TEMPERATURE RANGE PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address, R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS ADDRESS 2048 TO ADDRESS 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS ADDRESS 2056 (0x0808)—GPIO PIN SETTING REGISTER ADDRESS 2057 TO ADDRESS 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS ADDRESS 2064 TO ADDRESS 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS ADDRESS 2069 TO ADDRESS 2073 (0x0815 TO 0x0819)—SAFELOAD ADDRESS REGISTERS ADDRESS 2074 AND ADDRESS 2075 (0x081A AND 0x081B)—DATA CAPTURE REGISTERS ADDRESS 2076 (0x081C)—DSP CORE CONTROL REGISTER ADDRESS 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER ADDRESS 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER ADDRESS 2080 AND ADDRESS 2081 (0x0820 AND 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS ADDRESS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL REGISTER ADDRESS 2084 (0x0824)—AUXILIARY ADC ENABLE REGISTER ADDRESS 2086 (0x0826)—OSCILLATOR POWER-DOWN REGISTER ADDRESS 2087 (0x0827)—DAC SETUP REGISTER MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS