Datasheet ADAU1761 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL |
| 页数 / 页 | 93 / 3 — Data Sheet. ADAU1761. REVISION HISTORY 7/2018—Rev. C to Rev. D. … |
| 修订版 | E |
| 文件格式/大小 | PDF / 1.4 Mb |
| 文件语言 | 英语 |
Data Sheet. ADAU1761. REVISION HISTORY 7/2018—Rev. C to Rev. D. 9/2010—Rev. B to Rev. C. 5/2010—Rev. A to Rev. B
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Data Sheet ADAU1761 REVISION HISTORY 7/2018—Rev. C to Rev. D
Changes to SPI Port Section .. 41 Changed tSODM Serial Port Parameter to tSOD Serial Port Changes to Serial Data Input/Output Ports Section and Parameter, Table 7 ... 11 Table25 .. 42 Changes to tSOD Serial Port Parameter, Table 7 .. 11 Added Figure 57 .. 42 Changes to Figure 3... 12 Changes to Architecture Section and Figure 67.. 45 Changes to Figure 7... 15 Added Startup Section .. 45 Updated Outline Dimensions .. 93 Changes to Parameter RAM Section and Data RAM Section .. 47 Changes to Ordering Guide ... 93 Changes to Table 33 .. 51 Changes to R2: Digital Microphone/Jack Detection Control,
9/2010—Rev. B to Rev. C
16,392 (0x4008) Section and Table 36 .. 54 Changes to Figure 1... 1 Changes to Table 42 .. 58 Changes to Table 43 .. 59
5/2010—Rev. A to Rev. B
Changes to R15: Serial Port Control 0, 16,405 (0x4015) Section Changes to Burst Mode Writing and Reading Section .. 38 and Table 49 ... 63 Changes to Table 33 .. 51 Change to Table 50 .. 64 Added R67: Dejitter Control, 16,438 (0x4036) Section ... 79 Changes to Table 51, R18: Converter Control 1, 16,408 (0x4018) Section, and Table 52 .. 65
12/2009—Rev. 0 to Rev. A
Changes to Table 60, R27: Playback L/R Mixer Right (Mixer 6) Changes to Features Section .. 1 Line Output Control, 16,417 (0x4021) Section, and Table 61... 71 Change to General Description Section ... 1 Changes to Table 62, R29: Playback Headphone Left Volume Changes to Table 1 .. 6 Control, 16,419 (0x4023) Section, and Table 63 ... 72 Change to Table 5 .. 10 Changes to Table 64 .. 73 Changes to Figure 6... 13 Changes to R42: Jack Detect Pin Control, 16,433 (0x4031) Changes to Table 10 .. 15 Section and Table 76 ... 79 Changes to Captions of Figure 15, Figure 16, Figure 18, and Changes to R57: DSP Sampling Rate Setting, 16,619 (0x40EB) Figure 19 ... 18 Section and Table 81 ... 81 Changes to Captions of Figure 21 and Figure 24 .. 19 Change to Table 85 .. 83 Added Figure 25; Renumbered Sequentially ... 19 Change to Table 88 .. 84 Change to Figure 26 .. 20 Changes to R66: Clock Enable 1, 16,634 (0x40FA) Section and Change to Figure 27 .. 21 Table 90 ... 85 Change to Figure 28 .. 22 Change to Theory of Operation Section .. 23
1/2009—Revision 0: Initial Version
Changes to Power Reduction Modes Section and Case 1: PLL Is Bypassed Section ... 24 Changes to PLL Lock Acquisition Section ... 25 Changes to Core Clock Section and Figure 30 .. 26 Change to Sampling Rates Section.. 27 Changes to Input Signal Paths Section and Figure 32 .. 29 Changes to Figure 33 and Figure 34 ... 30 Changes to ADC Full-Scale Level Section ... 31 Change to Automatic Level Control (ALC) Section ... 32 Changes to Output Signal Paths Section .. 35 Changes to Headphone Output Section ... 36 Changes to Jack Detection Section, Pop-and-Click Suppression Section, and Line Outputs Section .. 37 Changes to Control Ports Section and I2C Port Section .. 38 Added Burst Mode Writing and Reading Section .. 38 Rev. D | Page 3 of 93 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Analog Performance Specifications Power Supply Specifications Typical Current Consumption Typical Power Management Measurements Digital Filters Digital Input/Output Specifications Digital Timing Specifications Digital Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics System Block Diagrams Theory of Operation Startup, Initialization, and Power Power-Up Sequence Power Reduction Modes Digital Power Supply Input/Output Power Supply Clock Generation and Management Case 1: PLL Is Bypassed Case 2: PLL Is Used PLL Lock Acquisition Clocking and Sampling Rates Core Clock Sampling Rates PLL Integer Mode Fractional Mode Record Signal Path Input Signal Paths Analog Microphone Inputs Analog Line Inputs Digital Microphone Input Microphone Bias Analog-to-Digital Converters ADC Full-Scale Level Digital ADC Volume Control High-Pass Filter Automatic Level Control (ALC) ALC Parameters Noise Gate Function Playback Signal Path Output Signal Paths Routing Flexibility Headphone Output Capless Headphone Configuration Headphone Output Power-Up/Power-Down Sequencing Ground-Centered Headphone Configuration Jack Detection Pop-and-Click Suppression Line Outputs Control Ports Burst Mode Writing and Reading I2C Port Addressing I2C Read and Write Operations SPI Port Chip Address R/WB Subaddress Data Bytes Serial Data Input/Output Ports Applications Information Power Supply Bypass Capacitors GSM Noise Filter Grounding Exposed Pad PCB Design DSP Core Signal Processing Architecture Program Counter Features Startup Numeric Formats Numeric Format 5.23 Programming Program RAM, Parameter RAM, and Data RAM Program RAM Parameter RAM Data RAM Read/Write Data Formats Software Safeload Software Slew General-Purpose Input/Output GPIO Pins Set from the Control Port Control Registers Control Register Details R0: Clock Control, 16,384 (0x4000) R1: PLL Control, 16,386 (0x4002) R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008) R3: Record Power Management, 16,393 (0x4009) R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A) R5: Record Mixer Left (Mixer 1) Control 1, 16,395 (0x400B) R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C) R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D) R8: Left Differential Input Volume Control, 16,398 (0x400E) R9: Right Differential Input Volume Control, 16,399 (0x400F) R10: Record Microphone Bias Control, 16,400 (0x4010) R11: ALC Control 0, 16,401 (0x4011) R12: ALC Control 1, 16,402 (0x4012) R13: ALC Control 2, 16,403 (0x4013) R14: ALC Control 3, 16,404 (0x4014) R15: Serial Port Control 0, 16,405 (0x4015) R16: Serial Port Control 1, 16,406 (0x4016) R17: Converter Control 0, 16,407 (0x4017) R18: Converter Control 1, 16,408 (0x4018) R19: ADC Control, 16,409 (0x4019) R20: Left Input Digital Volume, 16,410 (0x401A) R21: Right Input Digital Volume, 16,411 (0x401B) R22: Playback Mixer Left (Mixer 3) Control 0, 16,412 (0x401C) R23: Playback Mixer Left (Mixer 3) Control 1, 16,413 (0x401D) R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E) R25: Playback Mixer Right (Mixer 4) Control 1, 16,415 (0x401F) R26: Playback L/R Mixer Left (Mixer 5) Line Output Control, 16,416 (0x4020) R27: Playback L/R Mixer Right (Mixer 6) Line Output Control, 16,417 (0x4021) R28: Playback L/R Mixer Mono Output (Mixer 7) Control, 16,418 (0x4022) R29: Playback Headphone Left Volume Control, 16,419 (0x4023) R30: Playback Headphone Right Volume Control, 16,420 (0x4024) R31: Playback Line Output Left Volume Control, 16,421 (0x4025) R32: Playback Line Output Right Volume Control, 16,422 (0x4026) R33: Playback Mono Output Control, 16,423 (0x4027) R34: Playback Pop/Click Suppression, 16,424 (0x4028) R35: Playback Power Management, 16,425 (0x4029) R36: DAC Control 0, 16,426 (0x402A) R37: DAC Control 1, 16,427 (0x402B) R38: DAC Control 2, 16,428 (0x402C) R39: Serial Port Pad Control, 16,429 (0x402D) R40: Control Port Pad Control 0, 16,431 (0x402F) R41: Control Port Pad Control 1, 16,432 (0x4030) R42: Jack Detect Pin Control, 16,433 (0x4031) R67: Dejitter Control, 16,438 (0x4036) R43 to R47: Cyclic Redundancy Check Registers, 16,576 to 16,580 (0x40C0 to 0x40C4) R48 to R51: GPIO Pin Control, 16,582 to 16,585 (0x40C6 to 0x40C9) R52 to R56: Watchdog Registers, 16,592 to 16,596 (0x40D0 to 0x40D4) R57: DSP Sampling Rate Setting, 16,619 (0x40EB) R58: Serial Input Route Control, 16,626 (0x40F2) R59: Serial Output Route Control, 16,627 (0x40F3) R60: Serial Data/GPIO Pin Configuration, 16,628 (0x40F4) R61: DSP Enable, 16,629 (0x40F5) R62: DSP Run, 16,630 (0x40F6) R63: DSP Slew Modes, 16,631 (0x40F7) R64: Serial Port Sampling Rate, 16,632 (0x40F8) R65: Clock Enable 0, 16,633 (0x40F9) R66: Clock Enable 1, 16,634 (0x40FA) Outline Dimensions Ordering Guide
Changes to SPI Port Section .. 41 Changed tSODM Serial Port Parameter to tSOD Serial Port Changes to Serial Data Input/Output Ports Section and Parameter, Table 7 ... 11 Table25 .. 42 Changes to tSOD Serial Port Parameter, Table 7 .. 11 Added Figure 57 .. 42 Changes to Figure 3... 12 Changes to Architecture Section and Figure 67.. 45 Changes to Figure 7... 15 Added Startup Section .. 45 Updated Outline Dimensions .. 93 Changes to Parameter RAM Section and Data RAM Section .. 47 Changes to Ordering Guide ... 93 Changes to Table 33 .. 51 Changes to R2: Digital Microphone/Jack Detection Control,
9/2010—Rev. B to Rev. C
16,392 (0x4008) Section and Table 36 .. 54 Changes to Figure 1... 1 Changes to Table 42 .. 58 Changes to Table 43 .. 59
5/2010—Rev. A to Rev. B
Changes to R15: Serial Port Control 0, 16,405 (0x4015) Section Changes to Burst Mode Writing and Reading Section .. 38 and Table 49 ... 63 Changes to Table 33 .. 51 Change to Table 50 .. 64 Added R67: Dejitter Control, 16,438 (0x4036) Section ... 79 Changes to Table 51, R18: Converter Control 1, 16,408 (0x4018) Section, and Table 52 .. 65
12/2009—Rev. 0 to Rev. A
Changes to Table 60, R27: Playback L/R Mixer Right (Mixer 6) Changes to Features Section .. 1 Line Output Control, 16,417 (0x4021) Section, and Table 61... 71 Change to General Description Section ... 1 Changes to Table 62, R29: Playback Headphone Left Volume Changes to Table 1 .. 6 Control, 16,419 (0x4023) Section, and Table 63 ... 72 Change to Table 5 .. 10 Changes to Table 64 .. 73 Changes to Figure 6... 13 Changes to R42: Jack Detect Pin Control, 16,433 (0x4031) Changes to Table 10 .. 15 Section and Table 76 ... 79 Changes to Captions of Figure 15, Figure 16, Figure 18, and Changes to R57: DSP Sampling Rate Setting, 16,619 (0x40EB) Figure 19 ... 18 Section and Table 81 ... 81 Changes to Captions of Figure 21 and Figure 24 .. 19 Change to Table 85 .. 83 Added Figure 25; Renumbered Sequentially ... 19 Change to Table 88 .. 84 Change to Figure 26 .. 20 Changes to R66: Clock Enable 1, 16,634 (0x40FA) Section and Change to Figure 27 .. 21 Table 90 ... 85 Change to Figure 28 .. 22 Change to Theory of Operation Section .. 23
1/2009—Revision 0: Initial Version
Changes to Power Reduction Modes Section and Case 1: PLL Is Bypassed Section ... 24 Changes to PLL Lock Acquisition Section ... 25 Changes to Core Clock Section and Figure 30 .. 26 Change to Sampling Rates Section.. 27 Changes to Input Signal Paths Section and Figure 32 .. 29 Changes to Figure 33 and Figure 34 ... 30 Changes to ADC Full-Scale Level Section ... 31 Change to Automatic Level Control (ALC) Section ... 32 Changes to Output Signal Paths Section .. 35 Changes to Headphone Output Section ... 36 Changes to Jack Detection Section, Pop-and-Click Suppression Section, and Line Outputs Section .. 37 Changes to Control Ports Section and I2C Port Section .. 38 Added Burst Mode Writing and Reading Section .. 38 Rev. D | Page 3 of 93 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Analog Performance Specifications Power Supply Specifications Typical Current Consumption Typical Power Management Measurements Digital Filters Digital Input/Output Specifications Digital Timing Specifications Digital Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics System Block Diagrams Theory of Operation Startup, Initialization, and Power Power-Up Sequence Power Reduction Modes Digital Power Supply Input/Output Power Supply Clock Generation and Management Case 1: PLL Is Bypassed Case 2: PLL Is Used PLL Lock Acquisition Clocking and Sampling Rates Core Clock Sampling Rates PLL Integer Mode Fractional Mode Record Signal Path Input Signal Paths Analog Microphone Inputs Analog Line Inputs Digital Microphone Input Microphone Bias Analog-to-Digital Converters ADC Full-Scale Level Digital ADC Volume Control High-Pass Filter Automatic Level Control (ALC) ALC Parameters Noise Gate Function Playback Signal Path Output Signal Paths Routing Flexibility Headphone Output Capless Headphone Configuration Headphone Output Power-Up/Power-Down Sequencing Ground-Centered Headphone Configuration Jack Detection Pop-and-Click Suppression Line Outputs Control Ports Burst Mode Writing and Reading I2C Port Addressing I2C Read and Write Operations SPI Port Chip Address R/WB Subaddress Data Bytes Serial Data Input/Output Ports Applications Information Power Supply Bypass Capacitors GSM Noise Filter Grounding Exposed Pad PCB Design DSP Core Signal Processing Architecture Program Counter Features Startup Numeric Formats Numeric Format 5.23 Programming Program RAM, Parameter RAM, and Data RAM Program RAM Parameter RAM Data RAM Read/Write Data Formats Software Safeload Software Slew General-Purpose Input/Output GPIO Pins Set from the Control Port Control Registers Control Register Details R0: Clock Control, 16,384 (0x4000) R1: PLL Control, 16,386 (0x4002) R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008) R3: Record Power Management, 16,393 (0x4009) R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A) R5: Record Mixer Left (Mixer 1) Control 1, 16,395 (0x400B) R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C) R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D) R8: Left Differential Input Volume Control, 16,398 (0x400E) R9: Right Differential Input Volume Control, 16,399 (0x400F) R10: Record Microphone Bias Control, 16,400 (0x4010) R11: ALC Control 0, 16,401 (0x4011) R12: ALC Control 1, 16,402 (0x4012) R13: ALC Control 2, 16,403 (0x4013) R14: ALC Control 3, 16,404 (0x4014) R15: Serial Port Control 0, 16,405 (0x4015) R16: Serial Port Control 1, 16,406 (0x4016) R17: Converter Control 0, 16,407 (0x4017) R18: Converter Control 1, 16,408 (0x4018) R19: ADC Control, 16,409 (0x4019) R20: Left Input Digital Volume, 16,410 (0x401A) R21: Right Input Digital Volume, 16,411 (0x401B) R22: Playback Mixer Left (Mixer 3) Control 0, 16,412 (0x401C) R23: Playback Mixer Left (Mixer 3) Control 1, 16,413 (0x401D) R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E) R25: Playback Mixer Right (Mixer 4) Control 1, 16,415 (0x401F) R26: Playback L/R Mixer Left (Mixer 5) Line Output Control, 16,416 (0x4020) R27: Playback L/R Mixer Right (Mixer 6) Line Output Control, 16,417 (0x4021) R28: Playback L/R Mixer Mono Output (Mixer 7) Control, 16,418 (0x4022) R29: Playback Headphone Left Volume Control, 16,419 (0x4023) R30: Playback Headphone Right Volume Control, 16,420 (0x4024) R31: Playback Line Output Left Volume Control, 16,421 (0x4025) R32: Playback Line Output Right Volume Control, 16,422 (0x4026) R33: Playback Mono Output Control, 16,423 (0x4027) R34: Playback Pop/Click Suppression, 16,424 (0x4028) R35: Playback Power Management, 16,425 (0x4029) R36: DAC Control 0, 16,426 (0x402A) R37: DAC Control 1, 16,427 (0x402B) R38: DAC Control 2, 16,428 (0x402C) R39: Serial Port Pad Control, 16,429 (0x402D) R40: Control Port Pad Control 0, 16,431 (0x402F) R41: Control Port Pad Control 1, 16,432 (0x4030) R42: Jack Detect Pin Control, 16,433 (0x4031) R67: Dejitter Control, 16,438 (0x4036) R43 to R47: Cyclic Redundancy Check Registers, 16,576 to 16,580 (0x40C0 to 0x40C4) R48 to R51: GPIO Pin Control, 16,582 to 16,585 (0x40C6 to 0x40C9) R52 to R56: Watchdog Registers, 16,592 to 16,596 (0x40D0 to 0x40D4) R57: DSP Sampling Rate Setting, 16,619 (0x40EB) R58: Serial Input Route Control, 16,626 (0x40F2) R59: Serial Output Route Control, 16,627 (0x40F3) R60: Serial Data/GPIO Pin Configuration, 16,628 (0x40F4) R61: DSP Enable, 16,629 (0x40F5) R62: DSP Run, 16,630 (0x40F6) R63: DSP Slew Modes, 16,631 (0x40F7) R64: Serial Port Sampling Rate, 16,632 (0x40F8) R65: Clock Enable 0, 16,633 (0x40F9) R66: Clock Enable 1, 16,634 (0x40FA) Outline Dimensions Ordering Guide