Datasheet ADAU1701 (Analog Devices) - 8

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ADAU1701 Data Sheet Limit Parameter tMIN tMAX Unit Test Conditions/Comments
MULTIPURPOSE PINS AND RESET tGRT 50 ns GPIO (MPx pins) rise time tGFT 50 ns GPIO (MPx pins) fall time tGIL 1.5 × 1/fS μs GPIO (MPx pins) input latency; time until high/low value is read by core tRLPW 20 ns RESET low pulse width 1 All timing specifications are given for the default (I2S) states of the serial input port and the serial output port (see Table 65).
Digital Timing Diagrams tBIH tLIH INPUT_BCLK tBIL tLIS INPUT_LRCLK tSIS SDATA_INx LEFT-JUSTIFIED MSB MSB – 1 MODE tSIH tSIS SDATA_INx I2S MODE MSB tSIH t t SIS SIS SDATA_INx RIGHT-JUSTIFIED MSB LSB MODE t t SIH SIH 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA)
2
16-BIT CLOCKS
-00
(16-BIT DATA)
12 64 0 Figure 2. Serial Input Port Timing
tCLS tCLH t t CLPH CCPL CLATCH tCCPH CCLK CDATA tCDH tCDS COUT t
4
COD
00 2- 41 06 Figure 3. SPI Port Timing Rev. C | Page 8 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER TEMPERATURE RANGE PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS 2056 (0x0808)—GPIO PIN SETTING REGISTER 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS 2076 (0x081C)—DSP CORE CONTROL REGISTER 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL 2084 (0x0824)—AUXILIARY ADC ENABLE 2086 (0x0826)—OSCILLATOR POWER-DOWN 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE