Datasheet LTC6957-1, LTC6957-2, LTC6957-3, LTC6957-4 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | Low Phase Noise, Dual Output Buffer/Driver/Logic Converter |
| 页数 / 页 | 38 / 1 — FEATURES. DESCRIPTION. Low Phase Noise Buffer/Driver. Optimized … |
| 文件格式/大小 | PDF / 1.4 Mb |
| 文件语言 | 英语 |
FEATURES. DESCRIPTION. Low Phase Noise Buffer/Driver. Optimized Conversion of Sine Wave Signals to. Logic Levels
该数据表的模型线
- LTC6957HMS-1#PBF LTC6957HMS-1#TRPBF LTC6957HMS-2#PBF LTC6957HMS-2#TRPBF LTC6957HMS-3#PBF LTC6957HMS-3#TRPBF LTC6957HMS-4#PBF LTC6957HMS-4#TRPBF LTC6957IDD-1#PBF LTC6957IDD-1#TRPBF LTC6957IDD-2#PBF LTC6957IDD-2#TRPBF LTC6957IDD-3#PBF LTC6957IDD-3#TRPBF LTC6957IDD-4#PBF LTC6957IDD-4#TRPBF LTC6957IMS-1#PBF LTC6957IMS-1#TRPBF LTC6957IMS-2#PBF LTC6957IMS-2#TRPBF LTC6957IMS-3#PBF LTC6957IMS-3#TRPBF LTC6957IMS-4#PBF LTC6957IMS-4#TRPBF
文件文字版本
LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4 Low Phase Noise, Dual Output Buffer/Driver/ Logic Converter
FEATURES DESCRIPTION
n
Low Phase Noise Buffer/Driver
The LTC®6957-1/LTC6957-2/LTC6957-3/LTC6957-4 is a n
Optimized Conversion of Sine Wave Signals to
family of very low phase noise, dual output AC signal
Logic Levels
buffer/driver/logic level translators. The input signal can n
Three Logic Output Types Available
be a sine wave or any logic level (≤2VP-P). There are four n
LVPECL
members of the family that differ in their output logic n
LVDS
signal type as follows: n
CMOS
LTC6957-1: LVPECL Logic Outputs n Additive Jitter 45fsRMS (LTC6957-1) n LTC6957-2: LVDS Logic Outputs Frequency Range Up to 300MHz n 3.15V to 3.45V Supply Operation LTC6957-3: CMOS Logic, In-Phase Outputs n Low Skew 3ps Typical LTC6957-4: CMOS Logic, Complementary Outputs n Fully Specified from –40°C to 125°C n 12-Lead MSOP and 3mm × 3mm DFN Packages The LTC6957 will buffer and distribute any logic signal with minimal additive noise, however, the part really
APPLICATIONS
excels at translating sine wave signals to logic levels. The n early amplifier stages have selectable lowpass filtering System Reference Frequency Distribution n to minimize the noise while still amplifying the signal to High Speed ADC, DAC, DDS Clock Driver n increase its slew rate. This input stage filtering/noise limit- Military and Secure Radio n ing is especially helpful in delivering the lowest possible Low Noise Timing Trigger n phase noise signal with slow slewing input signals such Broadband Wireless Transceiver n as a typical 10MHz sine wave system reference. High Speed Data Acquisition n All registered trademarks and trademarks are the property of their respective owners. Protected Medical Imaging by U.S. Patents 7969189 and 8319551. n Test and Measurement
TYPICAL APPLICATION
3.3V 0.1µF
Additive Phase Noise at 100MHz
–140 SINGLE-ENDED SINE WAVE INPUT AT +7dBm (500mVRMS) V+ SD1 –145 FILTA = FILTB = GND FILTA FILTB /Hz) TO PLL CHIPS LTC6957-2 (LVDS) 100MHz OUT1 OR SYSTEM –150 +7dBm 10nF SINE WAVE SAMPLING CLOCKS LTC6957-4 (CMOS) IN+ OCXO IN– –155 50Ω 10nF PHASE NOISE (dBc OUT2 –160 LTC6957-3 (CMOS) LTC6957-1 (LVPECL) GND SD2 –165 6957 TA01a 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 69571234 TA01b 6957fb For more information www.linear.com/LTC6957-1 1 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagrams Timing Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
FEATURES DESCRIPTION
n
Low Phase Noise Buffer/Driver
The LTC®6957-1/LTC6957-2/LTC6957-3/LTC6957-4 is a n
Optimized Conversion of Sine Wave Signals to
family of very low phase noise, dual output AC signal
Logic Levels
buffer/driver/logic level translators. The input signal can n
Three Logic Output Types Available
be a sine wave or any logic level (≤2VP-P). There are four n
LVPECL
members of the family that differ in their output logic n
LVDS
signal type as follows: n
CMOS
LTC6957-1: LVPECL Logic Outputs n Additive Jitter 45fsRMS (LTC6957-1) n LTC6957-2: LVDS Logic Outputs Frequency Range Up to 300MHz n 3.15V to 3.45V Supply Operation LTC6957-3: CMOS Logic, In-Phase Outputs n Low Skew 3ps Typical LTC6957-4: CMOS Logic, Complementary Outputs n Fully Specified from –40°C to 125°C n 12-Lead MSOP and 3mm × 3mm DFN Packages The LTC6957 will buffer and distribute any logic signal with minimal additive noise, however, the part really
APPLICATIONS
excels at translating sine wave signals to logic levels. The n early amplifier stages have selectable lowpass filtering System Reference Frequency Distribution n to minimize the noise while still amplifying the signal to High Speed ADC, DAC, DDS Clock Driver n increase its slew rate. This input stage filtering/noise limit- Military and Secure Radio n ing is especially helpful in delivering the lowest possible Low Noise Timing Trigger n phase noise signal with slow slewing input signals such Broadband Wireless Transceiver n as a typical 10MHz sine wave system reference. High Speed Data Acquisition n All registered trademarks and trademarks are the property of their respective owners. Protected Medical Imaging by U.S. Patents 7969189 and 8319551. n Test and Measurement
TYPICAL APPLICATION
3.3V 0.1µF
Additive Phase Noise at 100MHz
–140 SINGLE-ENDED SINE WAVE INPUT AT +7dBm (500mVRMS) V+ SD1 –145 FILTA = FILTB = GND FILTA FILTB /Hz) TO PLL CHIPS LTC6957-2 (LVDS) 100MHz OUT1 OR SYSTEM –150 +7dBm 10nF SINE WAVE SAMPLING CLOCKS LTC6957-4 (CMOS) IN+ OCXO IN– –155 50Ω 10nF PHASE NOISE (dBc OUT2 –160 LTC6957-3 (CMOS) LTC6957-1 (LVPECL) GND SD2 –165 6957 TA01a 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 69571234 TA01b 6957fb For more information www.linear.com/LTC6957-1 1 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagrams Timing Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts