Datasheet HMC988LP3E (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | Programmable Clock Divider & Delay, DC - 4 GHz |
| 页数 / 页 | 22 / 2 — HMC988LP3E. PROGRAMMABLE CLOCK DIVIDER AND DELAY. DC - 4 GHz. Table 1. … |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
HMC988LP3E. PROGRAMMABLE CLOCK DIVIDER AND DELAY. DC - 4 GHz. Table 1. Electrical Specifications
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HMC988LP3E
v04.1014
PROGRAMMABLE CLOCK DIVIDER AND DELAY DC - 4 GHz Table 1. Electrical Specifications
unless otherwise specified: t = +25 °C. Current consumptions assumes fine adjustable delay is disabled. Phase noise degrades approximately 15 db if using fine delay adjustment. t Parameter Conditions Min typ. Max units M osCP/n input Frequency range DC 4 GHz s DiVP/n output Frequency range DC 4 GHz Divide ratios 1/2/4/8/16/32 Maximum Fine Delay Adjust Frequency DC 1 GHz n - VDD with on-chip regulator +3.7 +4.5 +5.5 V io VDD bypass on-chip regulator +3.1 +3.3 +3.5 V t 0.800 input swing (lVPECl or AC) Vpp see Figure 9 u Measured into a 50ohm 0.8 (single ended) Vpp ib load output swing (lVPECl) [1] r Measured into a 50ohm 1.6 (differential) Vppd load t rise/Fall time (lVPECl out) 20%/80% 90 ps is osCP/n input Commom Mode DC bias [2] +1.6 +2 +2.5 V DiVP/n output Common Mode Voltage [1] +2 V k D C Phase noise (@100 MHz offset) [3] @ 100 MHz output -170 @ 500 MHz output dbc/Hz lo -168 @ 1 GHz output C -166 @ 2 GHz output -164 Jitter Density [4] @ 100 MHz output 7.1 @ 500 MHz output 1.8 asec/√Hz @ 1 GHz output 1.1 @ 2 GHz output 0.7 integrated Jitter (12k - 20MHz) [5] @ 100 MHz output 32 @ 500 MHz output [6] 8 fsec @ 1 GHz output [6] 5 @ 2 GHz output [6] 3.2 noise Floor = FoM (Figure of Merit) noise Floor -254 dbc/Hz FoM+10log(Fout) input Coarse Delay Adjustment range 1/2 to ∞ *tinPut Cycles 60 steps of ~ 20 ps; Delay compresses with increasing frequency. Fine Delay Adjustment range [7] see Figure 6. With 300 1500 ps divider bypassed maxi- mum frequency limited to 650MHz Fine Delay Adjustment resolution 20 ps Fine Delay Adjustment step Count 60 Psrr [8] AM -70 -80 dbc With regulator PM -80 -92 dbc Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com
2
Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 p 3 o plica r a tio p n S p u s p @ po h rt itt : P ite ho . n c e o : 1m -800-ANALOG-D
v04.1014
PROGRAMMABLE CLOCK DIVIDER AND DELAY DC - 4 GHz Table 1. Electrical Specifications
unless otherwise specified: t = +25 °C. Current consumptions assumes fine adjustable delay is disabled. Phase noise degrades approximately 15 db if using fine delay adjustment. t Parameter Conditions Min typ. Max units M osCP/n input Frequency range DC 4 GHz s DiVP/n output Frequency range DC 4 GHz Divide ratios 1/2/4/8/16/32 Maximum Fine Delay Adjust Frequency DC 1 GHz n - VDD with on-chip regulator +3.7 +4.5 +5.5 V io VDD bypass on-chip regulator +3.1 +3.3 +3.5 V t 0.800 input swing (lVPECl or AC) Vpp see Figure 9 u Measured into a 50ohm 0.8 (single ended) Vpp ib load output swing (lVPECl) [1] r Measured into a 50ohm 1.6 (differential) Vppd load t rise/Fall time (lVPECl out) 20%/80% 90 ps is osCP/n input Commom Mode DC bias [2] +1.6 +2 +2.5 V DiVP/n output Common Mode Voltage [1] +2 V k D C Phase noise (@100 MHz offset) [3] @ 100 MHz output -170 @ 500 MHz output dbc/Hz lo -168 @ 1 GHz output C -166 @ 2 GHz output -164 Jitter Density [4] @ 100 MHz output 7.1 @ 500 MHz output 1.8 asec/√Hz @ 1 GHz output 1.1 @ 2 GHz output 0.7 integrated Jitter (12k - 20MHz) [5] @ 100 MHz output 32 @ 500 MHz output [6] 8 fsec @ 1 GHz output [6] 5 @ 2 GHz output [6] 3.2 noise Floor = FoM (Figure of Merit) noise Floor -254 dbc/Hz FoM+10log(Fout) input Coarse Delay Adjustment range 1/2 to ∞ *tinPut Cycles 60 steps of ~ 20 ps; Delay compresses with increasing frequency. Fine Delay Adjustment range [7] see Figure 6. With 300 1500 ps divider bypassed maxi- mum frequency limited to 650MHz Fine Delay Adjustment resolution 20 ps Fine Delay Adjustment step Count 60 Psrr [8] AM -70 -80 dbc With regulator PM -80 -92 dbc Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com
2
Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 p 3 o plica r a tio p n S p u s p @ po h rt itt : P ite ho . n c e o : 1m -800-ANALOG-D