Datasheet ADSP-SC570, ADSP-SC571, ADSP-SC572, ADSP-SC573, ADSP-21571, ADSP-21573 (Analog Devices) - 9

ADSP-SC570/SC571/SC572/ SC573/ADSP-21571/21573 Single-Instruction, Multiple Data (SIMD) Computational Data Register File Engine
Each processing element contains a general-purpose data regis- The SHARC+ core contains two computational processing ele- ter file. The register files transfer data between the computation ments that operate as a single-instruction, multiple data (SIMD) units and the data buses, and store intermediate results. These engine. 10-port, 32-register register files (16 primary, 16 secondary), combined with the enhanced Harvard architecture of the pro- The processing elements are referred to as PEx and PEy data cessor, allow unconstrained data flow between computation registers and each contain an arithmetic logic unit (ALU), mul- units and internal memory. The registers in the PEx data regis- tiplier, shifter, and register file. PEx is always active and PEy is ter file are referred to as R0–R15 and in the PEy data register file enabled by setting the PEYEN mode bit in the mode control as S0–S15. register (MODE1). SIMD mode allows the processors to execute the same instruc-
Context Switch
tion in both processing elements, but each processing element Many of the registers of the processor have secondary registers operates on different data. This architecture efficiently executes that can activate during interrupt servicing for a fast context math intensive DSP algorithms. In addition to all the features of switch. The data, DAG, and multiplier result registers have sec- previous generation SHARC cores, the SHARC+ core also pro- ondary registers. The primary registers are active at reset, while vides a new and simpler way to execute an instruction only on control bits in MODE1 activate the secondary registers. the PEy data register.
Universal Registers
SIMD mode also affects the way data transfers between memory and the processing elements because to sustain computational General-purpose tasks use the universal registers. The four operation in the processing elements requires twice the data USTAT registers allow easy bit manipulations (set, clear, toggle, bandwidth. Therefore, entering SIMD mode doubles the band- test, XOR) for all control and status peripheral registers. width between memory and the processing elements. When The data bus exchange register (PX) permits data to pass using the DAGs to transfer data in SIMD mode, two data values between the 64-bit PM data bus and the 64-bit DM data bus or transfer with each memory or register file access. between the 40-bit register file and the PM or DM data bus.
Independent Parallel Computation Units
These registers contain hardware to handle the data width difference. Within each processing element is a set of pipelined computa- tional units. The computational units consist of a multiplier,
Data Address Generators (DAG) With Zero-Overhead
arithmetic/logic unit (ALU), and shifter. These units are
Hardware Circular Buffer Support
arranged in parallel, maximizing computational throughput. For indirect addressing and implementing circular data buffers These computational units support IEEE 32-bit single-precision in hardware, the ADSP-SC57x/ADSP-2157x processor uses the floating-point, 40-bit extended-precision floating-point, IEEE two data address generators (DAGs). Circular buffers allow effi- 64-bit double-precision floating-point, and 32-bit fixed-point cient programming of delay lines and other data structures data formats. required in digital signal processing, and are commonly used in A multifunction instruction set supports parallel execution of digital filters and fast Fourier transforms (FFT). The two DAGs the ALU and multiplier operations. In SIMD mode, the parallel of the processors contain sufficient registers to allow the cre- ALU and multiplier operations occur in both processing ele- ation of up to 32 circular buffers (16 primary register sets and ments per core. 16 secondary sets). The DAGs automatically handle address All processing operations take one cycle to complete. For all pointer wraparound, reduce overhead, increase performance, floating-point operations, the processor takes two cycles to and simplify implementation. Circular buffers can start and end complete in case of data dependency. Double-precision float- at any memory location. ing-point data take two to six cycles to complete. The processor
Flexible Instruction Set Architecture (ISA)
stalls for the appropriate number of cycles for an interlocked pipeline plus data dependency check. The flexible instruction set architecture (ISA), a 48-bit instruc- tion word, accommodates various parallel operations for
Core Timer
concise programming. For example, the processors can condi- Each SHARC+ processor core also has a timer. This extra timer tionally execute a multiply, an add, and a subtract in both is clocked by the internal processor clock and is typically used as processing elements while branching and fetching up to four a system tick clock for generating periodic operating system 32-bit values from memory—all in a single instruction. Addi- interrupts. tionally, the double-precision floating-point instruction set is an addition to the SHARC+ core. Rev. B | Page 9 of 142 | June 2018 Document Outline System Features Memory Additional Features Table Of Contents Revision History General Description ARM Cortex-A5 Processor Generic Interrupt Controller (GIC), PL390 (ADSP-SC57x Only) Generic Interrupt Controller Port0 (GICPORT0) Generic Interrupt Controller Port1 (GICPORT1) L2 Cache Controller, PL310 (ADSP-SC57x Only) SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory SHARC+ Core L1 Memory in Multiprocessor Space One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features ARM TrustZone Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Parity Protected ARM L1 Cache Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Enhanced Parallel Peripheral Interface (EPPI) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Link Port (LP) ADC Control Module (ACM) Interface Ethernet Media Access Controller (EMAC) Audio Video Bridging (AVB) Support Precision Time Protocol (PTP) IEEE 1588 Support Controller Area Network (CAN) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Housekeeping Analog-to-Digital Converter (HADC) USB 2.0 On the Go (OTG) Dual-Role Device Controller (BGA Only) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts Mobile Storage Interface (MSI) System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator and USB Crystal Oscillator Clock Distribution Unit (CDU) Power-Up Clock Out/External Clock Booting Thermal Monitoring Unit (TMU) Power Supplies Power Management Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages (BSPs) for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 176-Lead LQFP Signal Descriptions GPIO Multiplexing for 176-Lead LQFP Package ADSP-SC57x/ADSP-2157x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Current from High Speed Peripheral Operation Data Transmission Current HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications TMU TMU Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing DDR3 SDRAM Clock and Control Cycle Timing DDR3 SDRAM Read Cycle Timing DDR3 SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface (EPPI) Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAI0 Pin to DAI0 Pin Direct Routing Up/Down Counter/Rotary Encoder Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) 10/100 EMAC Timing 10/100/1000 EMAC Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Mobile Storage Interface (MSI) Controller Timing Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 176-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide