Datasheet ADSP-21477, ADSP-21478, ADSP-21479 (Analog Devices) - 5

ADSP-21477 /ADSP-21478 /ADSP-21479
buses and on-chip instruction cache, the processor can simulta- neously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. S
JTAG FLAG TIMER INTERRUPT CACHE SIMD Core PM ADDRESS 24 DMD/PMD 64 5 STAGE PROGRAM SEQUENCER PM DATA 48 DAG1 DAG2 16×32 16×32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 USTAT 4×32-BIT PM DATA 64 PX DM DATA 64 64-BIT RF DATA RF SWAP MULTIPLIER SHIFTER ALU Rx/Fx Sx/SFx ALU SHIFTER MULTIPLIER PEx PEy 16×40-BIT 16×40-BIT MRF MRB MSB MSF 80-BIT 80-BIT ASTATx ASTATy 80-BIT 80-BIT STYKx STYKy
Figure 2. SHARC Core Block Diagram
Instruction Cache
primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase The processor includes an on-chip instruction cache that performance, and simplify implementation. Circular buffers can enables three-bus operation for fetching an instruction and four start and end at any memory location. data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This
Flexible Instruction Set
cache allows full speed execution of core looped operations such as digital filter multiply-accumulates, and FFT butterfly The 48-bit instruction word accommodates a variety of parallel processing. operations, for concise programming. For example, the processors can conditionally execute a multiply, an add, and a
Data Address Generators with Zero-Overhead Hardware
subtract in both processing elements while branching and fetch-
Circular Buffer Support
ing up to four 32-bit values from memory—all in a single instruction. The processor’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers
Variable Instruction Set Architecture (VISA)
in hardware. Circular buffers allow efficient programming of In addition to supporting the standard 48-bit instructions from delay lines and other data structures required in digital signal previous SHARC processors, the processors support new processing, and are commonly used in digital filters and Fourier instructions of 16 and 32 bits. This feature, called Variable transforms. The two DAGs of the processors contain sufficient Instruction Set Architecture (VISA), drops redundant/unused registers to allow the creation of up to 32 circular buffers (16 Rev. D | Page 5 of 76 | April 2017 Document Outline SHARC Processor Summary Revision History Product Application Restriction General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth ROM Based Security Digital Transmission Content Protection Family Peripheral Architecture External Memory External Port SIMD Access to External Memory VISA and ISA Access to External Memory SDRAM Controller Asynchronous Memory Controller External Port Throughput MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Pulse-Width Modulation Timers 2-Wire Interface Port (TWI) Shift Register I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer (WDT) Real-Time Clock System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Maximum Power Dissipation Package Information ESD Sensitivity Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Shift Register Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-LFCSP_VQ Lead Assignment 100-LQFP_EP Lead Assignment 196-BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide