Datasheet ADSP-21467, ADSP-21469 (Analog Devices) - 9

ADSP-21467 /ADSP-21469 Asynchronous Sample Rate Converter UART Port
The asynchronous sample rate converter (ASRC) contains four The processors provide a full-duplex Universal Asynchronous ASRC blocks, is the same core as that used in the AD1896 192 Receiver/Transmitter (UART) port, which is fully compatible kHz stereo asynchronous sample rate converter, and provides with PC-standard UARTs. The UART port provides a simpli- up to 128 dB SNR. The ASRC block is used to perform synchro- fied UART interface to other peripherals or hosts, supporting nous or asynchronous sample rate conversion across full-duplex, DMA-supported, asynchronous transfers of serial independent stereo channels, without using internal processor data. The UART also has multiprocessor communication capa- resources. The four SRC blocks can also be configured to oper- bility using 9-bit address detection. This allows it to be used in ate together to convert multichannel audio data without phase multidrop networks through the RS-485 data interface mismatches. Finally, the ASRC can be used to clean up audio standard. The UART port also includes support for 5 to 8 data data from jittery clock sources such as the S/PDIF receiver. bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation:
Input Data Port
• PIO (programmed I/O) – The processors send or receive The IDP provides up to eight serial input channels—each with data by writing or reading I/O-mapped UART registers. its own clock, frame sync, and data inputs. The eight channels The data is double-buffered on both transmit and receive. are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided • DMA (direct memory access) – The DMA controller trans- into two 32-bit words. The serial protocol is designed to receive fers both transmit and receive data. This reduces the audio channels in I2S, left-justified sample pair, or right-justified number and frequency of interrupts required to transfer mode. One frame sync cycle indicates one 64-bit left/right pair, data to and from memory. but data is sent to the FIFO as 32-bit words (that is, one-half of a
Timers
frame at a time). The processors support 24- and 32-bit I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right- The processors have a total of three timers: a core timer that can justified formats. generate periodic software interrupts and two general- purpose timers that can generate periodic interrupts and be
Precision Clock Generators
independently set to operate in one of three modes: The precision clock generators (PCG) consist of four units—A, • Pulse waveform generation mode B, C, and D, each of which generates a pair of signals (clock and • Pulse width count/capture mode frame sync) derived from a clock input signal. The units are identical in functionality and operate independently of each • External event watchdog mode other. The two signals generated by each unit are normally used The core timer can be configured to use FLAG3 as a timer as a serial bit clock/frame sync pair. expired signal, and each general-purpose timer has one bidirec- tional pin and four registers that implement its mode of
Digital Peripheral Interface (DPI)
operation. A single control and status register enables or dis- The digital peripheral interface provides connections to two ables both general-purpose timers independently. serial peripheral interface (SPI) ports, one universal asynchro- nous receiver-transmitter (UART), 12 flags, a 2-wire interface
2-Wire Interface Port (TWI)
(TWI), and two general-purpose timers. The DPI includes the The TWI is a bidirectional, 2-wire serial bus used to move 8-bit peripherals described in the following sections. data while maintaining compliance with the I2C bus protocol. The TWI master incorporates the following features:
Serial Peripheral Interface
• 7-bit addressing The processors contain two serial peripheral interface ports (SPI). The SPI is an industry-standard synchronous serial link, • Simultaneous master and slave operation on multiple enabling the SPI-compatible port to communicate with other device systems with support for multi master data SPI compatible devices. The SPI consists of two data pins, one arbitration device select pin, and one clock pin. It is a full-duplex • Digital filtering and timed event processing synchronous serial interface, supporting both master and slave • 100 kbps and 400 kbps data rates modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, • Low interrupt rate either acting as a master or slave device. The SPI-compatible
I/O Processor Features
peripheral implementation also features programmable baud rate, clock phase, and polarities. The SPI-compatible port uses Automotive versions of the I/O processor provide 67 channels open-drain drivers to support a multimaster configuration and of DMA, while standard versions provide 36 channels of DMA, to avoid data contention. as well as an extensive set of peripherals that are described in the following sections. Rev. B | Page 9 of 76 | March 2013 Document Outline Summary Table Of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth Nonsecured ROM ROM-Based Security Digital Transmission Content Protection Family Peripheral Architecture External Port External Memory SIMD Access to External Memory VISA and ISA Access to External Memory Shared External Memory DDR2 Support DDR2 DRAM Controller Asynchronous Memory Controller External Port Throughput Link Ports MediaLB Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral Interface UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA IIR Accelerator FFT Accelerator FIR Accelerator System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing AMI Read AMI Write Shared Memory Bus Request Link Ports Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation (PWM) Generators S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Test Conditions Output Drive Currents Capacitive Loading Thermal Characteristics Thermal Diode CSP_BGA Ball Assignment—Automotive Models CSP_BGA Ball Assignment—Standard Models Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide