Datasheet ADSP-21371, ADSP-21375 (Analog Devices) - 7

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ADSP-21371 /ADSP-21375 Table 4. ADSP-21375 Internal Memory Space IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 bits) Instruction Word (48 bits) Normal Word (32 bits) Short Word (16 bits)
BLOCK 0 ROM BLOCK 0 ROM BLOCK 0 ROM BLOCK 0 ROM 0x0004 0000–0x0004 3FFF 0x0008 0000–0x0008 5554 0x0008 0000–0x0008 7FFF 0x0010 0000–0x0010 FFFF Reserved Reserved Reserved Reserved 0x0004 4000–0x0004 BFFF 0x0008 5555–0x0008 FFFF 0x0008 8000–0x0009 7FFF 0x0011 0000–0x0012 FFFF BLOCK 0 RAM BLOCK 0 RAM BLOCK 0 RAM BLOCK 0 RAM 0x0004 C000–0x0004 C7FF 0x0009 0000–0x0009 0AA9 0x0009 8000–0x0009 8FFF 0x0013 0000–0x0013 1FFF Reserved Reserved Reserved Reserved 0x0004 C800–0x0004 FFFF 0x0009 0AAA–0x0009 FFFF 0x0009 9000–0x0009 FFFF 0x0013 2000–0x0013 FFFF BLOCK 1 ROM BLOCK 1 ROM BLOCK 1 ROM BLOCK 1 ROM 0x0005 0000–0x0005 3FFF 0x000A 0000–0x000A 5554 0x000A 0000–0x000A 7FFF 0x0014 0000–0x0014 FFFF Reserved Reserved Reserved Reserved 0x0005 4000–0x0005 BFFF 0x000A 5555–0x000A FFFF 0x000A 8000–0x000B 7FFF 0x0015 0000–0x0016 FFFF BLOCK 1 RAM BLOCK 1 RAM BLOCK 1 RAM BLOCK 1 RAM 0x0005 C000–0x0005 C7FF 0x000B 0000–0x000B 0AA9 0x000B 8000–0x000B 8FFF 0x0017 0000–0x0017 1FFF Reserved Reserved Reserved Reserved 0x0005 C800–0x0005 FFFF 0x000B 0AAA–0x000B FFFF 0x000B 9000–0x000B FFFF 0x0017 2000–0x0017 FFFF BLOCK 2 RAM BLOCK 2 RAM BLOCK 2 RAM BLOCK 2 RAM 0x0006 0000–0x0006 07FF 0x000C 0000–0x000C 0AA9 0x000C 0000–0x000C 0FFF 0x0018 0000–0x0018 1FFF Reserved Reserved Reserved Reserved 0x0006 0800–0x0006 FFFF 0x000C 0AAA–0x000D FFFF 0x000C 1000–0x000D FFFF 0x0018 2000–0x001B FFFF BLOCK 3 RAM BLOCK 3 RAM BLOCK 3 RAM BLOCK 3 RAM 0x0007 0000–0x0007 07FF 0x000E 0000–0x000E 0AA9 0x000E 0000–0x000E 0FFF 0x001C 0000–0x001C 1FFF Reserved Reserved Reserved Reserved 0x0007 0800–0x0007 FFFF 0x000E 0AAA–0x000F FFFF 0x000E 1000–0x000F FFFF 0x001C 2000–0x001F FFFF
SDRAM Controller Table 5. External Memory for SDRAM Addresses
The SDRAM controller provides an interface to up to four sepa-
Bank Size in Words Address Range
rate banks of industry-standard SDRAM devices or DIMMs. Bank 0 62M 0x0020 0000–0x03FF FFFF Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to Bank 1 64M 0x0400 0000–0x07FF FFFF contain between 16M bytes and 256M bytes of memory. Bank 2 64M 0x0800 0000–0x0BFF FFFF SDRAM external memory address space is shown in Table 5. Bank 3 64M 0x0C00 0000–0x0FFF FFFF The controller maintains all of the banks as a contiguous address space so that the processor sees this as a single address Note that the external memory bank addresses shown in Table 5 space, even if different size devices are used in the are for normal word accesses. If 48-bit instructions are placed in different banks. any such bank (with two instructions packed into three 32-bit locations), then care must be taken to map data buffers in the A set of programmable timing parameters is available to config- same bank. For example, if 2k instructions are placed starting at ure the SDRAM banks to support slower memory devices. The the bank 0 base address (0x0020 0000), then the data buffers can memory banks can be configured as 16 bits wide or as be placed starting at an address that is offset by 3k words 32 bits wide. The SDRAM controller address, data, clock, and (0x0020 0C00). command pins can drive loads up to 30 pF. For larger memory systems, the SDRAM controller external buffer timing should
External Memory Code Execution
be selected and external buffering should be provided so that the The program sequencer can execute code directly from external load on the SDRAM controller pins does not exceed 30 pF. memory bank 0 (SRAM, SDRAM) over the 48-bit external port data bus (EPD). This allows a reduction in internal memory size, thereby reducing the die area. Because instructions on the Rev. D | Page 7 of 56 | April 2013 Document Outline Summary Dedicated Audio Components Table Of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of an Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Code Execution External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Input Data Port (IDP) Precision Clock Generator (PCG) Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions ADSP-21371/ADSP-21375 Specifications Operating Conditions Electrical Characteristics Package Information Maximum Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Core Timer Interrupts Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing Memory Read—Bus Master Memory Write—Bus Master Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing TWI Controller Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 208-Lead LQFP_EP Pinout Package Dimensions Automotive Products Ordering Guide