Datasheet ADSP-21261, ADSP-21262, ADSP-21266 (Analog Devices)

link to page 45 link to page 4
SHARC Embedded Processor ADSP-21261 /ADSP-21262 /ADSP-21266 SUMMARY High performance 32-bit/40-bit floating-point processor Single-instruction multiple-data (SIMD) computational archi- optimized for high performance audio processing tecture—two 32-bit IEEE floating-point/32-bit fixed-point/ Code compatibility—at assembly level, uses the same 40-bit extended precision floating-point computational instruction set as other SHARC DSPs units, each with a multiplier, ALU, shifter, and register file Processes high performance audio while enabling low High bandwidth I/O—a parallel port, an SPI port, 6 serial system costs ports, a Digital application interface (DAI), and JTAG Audio decoders and postprocessor algorithms support DAI incorporates two precision clock generators (PCGs), an nonvolatile memory that can be configured to contain a input data port (IDP) that includes a parallel data acquisi- combination of PCM 96 kHz, Dolby Digital, Dolby Digital tion port (PDAP), and 3 programmable timers, all under Surround EX, DTS-ES Discrete 6.1, DTS-ES Matrix 6.1, DTS software control by the signal routing unit (SRU) 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA- On-chip memory—up to 2M bits on-chip SRAM and a dedi- PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and cated 4M bits on-chip mask-programmable ROM DTS Neo:6 The ADSP-2126x processors are available with a 150 MHz or a Various multichannel surround sound decoders are con- 200 MHz core instruction rate. For complete ordering tained in ROM. For configurations of decoder algorithms, information, see Ordering Guide on Page 45 . see Table 3 on Page 4 . CORE PROCESSOR DUAL PORTED MEMORY DUAL PORTED MEMORY BLOCK 0 BLO CK 1 INSTRUCTION TIMER CACHE SRAM SRAM 32
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48-BIT 1M BIT ROM 1M BI T ROM 2M BI T 2M BIT DAG1 DAG2 PROG RAM 8
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32 8
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32 SEQ UE NCER ADDR DATA ADDR DATA PM ADDRESS BUS 32 DM ADDRESS BUS 32 64 PM DATA BUS 64 DM DATA BUS I OD IOA (32) (19) PX REGI STER DMA CONTRO LLER 4 2 2 C HA N N ELS GPIO FLAGS/ PROCESSING P RO CESSI NG ELEMENT IRQ /TIMEXP ELEMENT 4 (PEX) (PEY) SPI PORT (1) 16 A D D R ES S/ D A TA BU S / GPIO 6 3 SERIAL PORTS (6) C ON TR OL/GPIO JTAG TES T & EMULATION PARALLEL IOP PORT 20 SI GNAL REGISTE RS I NPUT RO UTI NG (MEMORY MAPPED) DATA PORTS (8) UNI T PARALLEL DATA ACQUISITION PORT CO NTROL, STATUS , DATA BUFFERS PRECISI ON CLOCK GENERATORS (2)
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3 PERIPHERAL TI MERS (3) DIGITAL AUDIO INTERFACE I/O PROCESSOR
Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
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Document Outline Summary Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Memory and I/O Interface Features Dual-Ported On-Chip Memory DMA Controller Digital Application Interface (DAI) Serial Ports Serial Peripheral (Compatible) Interface Parallel Port Timers ROM-Based Security Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Address Data Pins as Flags Boot Modes Core Instruction Rate to CLKIN Ratio Modes Address Data Modes Product Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin-to-Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) SPI Interface Protocol—Master SPI Interface Protocol—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Environmental Conditions Thermal Characteristics 144-Lead LQFP Pin Configurations 136-Ball BGA Pin Configurations Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide