Datasheet HVLED001B (STMicroelectronics) - 7
| 制造商 | STMicroelectronics |
| 描述 | DS12748: High power factor flyback controller with constant voltage primary-sensing and ultra-low standby consumption |
| 页数 / 页 | 33 / 7 — HVLED001B. Pin settings. Table 2. Pin description (continued). Symbol … |
| 修订版 | 1.0 |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
HVLED001B. Pin settings. Table 2. Pin description (continued). Symbol Pin. Description
该数据表的模型线
文件文字版本
HVLED001B Pin settings Table 2. Pin description (continued) Symbol Pin Description
Gate driver output. GD 9 The output stage is able to drive the power MOSFET's and IGBT's gate. Supply voltage of the IC. Internal UVLO logic prevents the operation at voltages that are insufficient for the efficient gate driving or signal processing. VCC 10 Both a bulk capacitor (typically around 22 μF) and a high frequency filter capacitor (100 nF ceramic, mounted as close as possible to the device) are connected between this pin and GND. An internal clamp structure prevents accidental low energy spikes damaging the device. DS12748 Rev 1 7/33 33 Document Outline Table 1. Device summary 1 Block diagram Figure 1. Block diagram 2 Typical application - HPF flyback Figure 2. Primary side regulated (PSR) application Figure 3. Secondary side regulated (SSR) application 3 Pin settings Figure 4. Pin connection Table 2. Pin description (continued) 4 Electrical data 4.1 Absolute maximum ratings Table 3. Absolute maximum ratings 4.2 Thermal data Table 4. Thermal data 4.3 Recommended operating conditions Table 5. Recommended operating conditions 5 Electrical characteristics Table 6. Electrical characteristics (continued) 6 Typical electrical characteristic 6.1 Parameter graphs Figure 5. ICC vs. Fsw @ VCC = 15V Figure 6. VCC,on and VCC,su vs. Tj Figure 7. Icharge and Icharge,su vs. Tj Figure 8. IFB,src and IFB,snk vs. Tj Figure 9. Vbm, Vbm2 and VOPTO,dis vs. Tj Figure 10. Tbm and Tbm2 vs. Tj Figure 11. VZCD,arm and VZCD,trig vs. Tj Figure 12. VCS,lim vs. Tj Figure 13. VREF,PSR vs. Tj Figure 14. IFB vs. VZCD sample Figure 15. TBLANK,min vs. Tj Figure 16. TBLANK,var vs. Tj 7 Application information 7.1 Operating modes Figure 17. High power factor flyback - Primary side regulated constant output voltage Figure 18. High power factor flyback – Secondary side regulated application 7.1.1 Start-up mode Figure 19. Initial start-up phase 7.1.2 Ramp-up mode 7.1.3 Active mode 7.1.4 Low consumption mode 7.1.5 Stop mode 7.2 Control loop Figure 20. Control loop blocks 7.2.1 Current sense input 7.2.2 Feedback input 7.2.3 Zero current detection Figure 21. TBLANK,var time vs. TOFF voltage Figure 22. TBLANK,var time vs. TOFF voltage 7.2.4 Primary side regulation feature Figure 23. PSR E/A small signal model 7.2.5 Burst mode operation 7.3 Gate driver 7.4 IC supply management 7.4.1 VCC supply management 7.4.2 High voltage startup Table 7. HVSU operating modes 7.5 Auto restart timer (ART) 7.6 Protections 7.6.1 Over current protection (OCP) 7.6.2 Input over voltage protection (I-OVP) 7.6.3 Brownout protection (BO) 7.6.4 Over power protection (OPP) 7.6.5 Output over voltage protection (oOVP) 7.7 Disable and monitor feature 8 Package information 8.1 SSOP10 package outline Figure 24. SSOP10 package mechanical data Table 8. SSOP10 package mechanical data 9 Revision history Table 9. Document history
Gate driver output. GD 9 The output stage is able to drive the power MOSFET's and IGBT's gate. Supply voltage of the IC. Internal UVLO logic prevents the operation at voltages that are insufficient for the efficient gate driving or signal processing. VCC 10 Both a bulk capacitor (typically around 22 μF) and a high frequency filter capacitor (100 nF ceramic, mounted as close as possible to the device) are connected between this pin and GND. An internal clamp structure prevents accidental low energy spikes damaging the device. DS12748 Rev 1 7/33 33 Document Outline Table 1. Device summary 1 Block diagram Figure 1. Block diagram 2 Typical application - HPF flyback Figure 2. Primary side regulated (PSR) application Figure 3. Secondary side regulated (SSR) application 3 Pin settings Figure 4. Pin connection Table 2. Pin description (continued) 4 Electrical data 4.1 Absolute maximum ratings Table 3. Absolute maximum ratings 4.2 Thermal data Table 4. Thermal data 4.3 Recommended operating conditions Table 5. Recommended operating conditions 5 Electrical characteristics Table 6. Electrical characteristics (continued) 6 Typical electrical characteristic 6.1 Parameter graphs Figure 5. ICC vs. Fsw @ VCC = 15V Figure 6. VCC,on and VCC,su vs. Tj Figure 7. Icharge and Icharge,su vs. Tj Figure 8. IFB,src and IFB,snk vs. Tj Figure 9. Vbm, Vbm2 and VOPTO,dis vs. Tj Figure 10. Tbm and Tbm2 vs. Tj Figure 11. VZCD,arm and VZCD,trig vs. Tj Figure 12. VCS,lim vs. Tj Figure 13. VREF,PSR vs. Tj Figure 14. IFB vs. VZCD sample Figure 15. TBLANK,min vs. Tj Figure 16. TBLANK,var vs. Tj 7 Application information 7.1 Operating modes Figure 17. High power factor flyback - Primary side regulated constant output voltage Figure 18. High power factor flyback – Secondary side regulated application 7.1.1 Start-up mode Figure 19. Initial start-up phase 7.1.2 Ramp-up mode 7.1.3 Active mode 7.1.4 Low consumption mode 7.1.5 Stop mode 7.2 Control loop Figure 20. Control loop blocks 7.2.1 Current sense input 7.2.2 Feedback input 7.2.3 Zero current detection Figure 21. TBLANK,var time vs. TOFF voltage Figure 22. TBLANK,var time vs. TOFF voltage 7.2.4 Primary side regulation feature Figure 23. PSR E/A small signal model 7.2.5 Burst mode operation 7.3 Gate driver 7.4 IC supply management 7.4.1 VCC supply management 7.4.2 High voltage startup Table 7. HVSU operating modes 7.5 Auto restart timer (ART) 7.6 Protections 7.6.1 Over current protection (OCP) 7.6.2 Input over voltage protection (I-OVP) 7.6.3 Brownout protection (BO) 7.6.4 Over power protection (OPP) 7.6.5 Output over voltage protection (oOVP) 7.7 Disable and monitor feature 8 Package information 8.1 SSOP10 package outline Figure 24. SSOP10 package mechanical data Table 8. SSOP10 package mechanical data 9 Revision history Table 9. Document history