Datasheet Si8921/22 (Silicon Labs) - 5
| 制造商 | Silicon Labs |
| 描述 | Isolated Amplifier for Current Shunt Measurement |
| 页数 / 页 | 30 / 5 — 3. Current Sense Application. Figure 3.1. Current Sense Application. … |
| 修订版 | 0.5 |
| 文件格式/大小 | PDF / 548 Kb |
| 文件语言 | 英语 |
3. Current Sense Application. Figure 3.1. Current Sense Application. silabs.com
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link to page 5 link to page 5 Si8921/22 Data Sheet Current Sense Application
3. Current Sense Application
In the driver circuit presented below, the Si8921 is used to amplify the voltage across the sense resistor, RSENSE, and transmit the analog signal to the low-voltage domain across an isolation barrier. Isolation is needed because the voltage of RSENSE with respect to ground will swing between 0 V and the high voltage rail connected to the drain of Q1. Floating Low Side High Gate Driver 3.3 to 5V Gate Driver Voltage Bus 24V Supply Supply Supply VDDA PWM Q1 C5 VOA 0.1uF GNDA VDDI GNDI DISABLE R6 VDDB DT VOB GNDB VDDI R3 Si8234 Q3 1.82K To Controller C3 D1 C2 C4 0.1uF 5.6V 0.1uF 0.1uF 1 VDDA VDDB 8 RSENSE R1 20 2 R4 AIP AOP 7 + C1 3 AIN AON 6 C6 ADC 10nF 4 R2 20 GNDA GNDB 5 R5 _ Load Si8921 Q2
Figure 3.1. Current Sense Application
The load in this application can be a motor winding or a similar inductive winding. In a three-phase motor drive application, this circuit would be repeated three times, one for each phase. RSENSE should be a small resistor value to reduce power loss. However, an ex- cessively low resistance will reduce the signal-to-noise ratio of the measurement. Si8921/22 offers two specified full-scale input options, ±62.5 mV (Si8921A/22A) and ±250 mV (Si8921B/22B), for optimizing the value of RSENSE. AIP and AIN connections to the RSENSE resistor should be made as close as possible to each end of the RSENSE resistor as trace resistance will add error to the measurement. The input to the Si8921/22 is differential, and the PCB traces back to the input pins should run in parallel. This ensures that any large noise transients that occur on the high-voltage side are coupled equally to the AIP and AIN pins and will be rejected by the Si8921/22 as a common-mode signal. The amplifier bandwidth of the Si8921/22 is approximately 600 kHz. If further input filtering is required, a passive, differential RC low- pass filter can be placed between RSENSE and the input pins. Values of R1 = R2 = 20 Ω and C1 = 10 nF, as shown in Figure 3.1 Current Sense Application on page 5, provides a cutoff at approximately 400 kHz. For the lowest gain error, R1 and R2 should always be less than 33 Ω to keep the source impedance sufficiently low compared to the Si8921/22 input impedance. The common-mode voltage of AIN and AIP must be greater than –0.2 V but less than 1 V with respect to GNDA. To meet this require- ment, connect GNDA of the Si8921/22 to one side of the RSENSE resistor. In this example, GNDA, RSENSE, the source of Q1, and the drain of Q2 are connected. The ground of the gate driver (Silicon Labs’ Si8234 in this circuit) is also commonly connected to the same node. The Q1 gate driver has a floating supply, 24 V in this example. Since the input and output of the Si8921/22 are galvanically isolated from each other, separate power supplies are necessary on each side. Q3, R3, C3, and D1 make a regulator circuit for powering the input side of the Si8921/22 from this floating supply. D1 establishes a voltage of 5.6 V at the base of Q3. R3 is selected to provide a Zener current of 10 mA for D1. C3 provides filtering at the base of Q3, and the emitter output of Q3 provides approximately 5 V to VDDA. C2 is a bypass capacitor for the supply and should be placed at the VDDA pin with its return trace connecting to the GNDA connection at RSENSE. C4, the local bypass capacitor for the B-side of Si8921/22, should be placed closed to VDDB supply pin with its return close to GNDB. The output signal at AOP and AON is differential with a nominal gain of 8.2 (Si8921B) or 34.8 (Si8921A) and common mode of 1.4 V. The outputs are sampled by a differential input ADC. Depending on the sample rate of the ADC, an anti-aliasing filter may be required. A simple anti-aliasing filter can be made from the passive components, R4, C6, and R5. The characteristics of this filter are dictated by the input topology and sampling frequency of the ADC. However, to ensure the Si8921 outputs are not overloaded, R4 = R5 > 5 kΩ and C6 can be calculated by the following equation: 1 C6 = 2 × π × (R4 + R5) × f3dB
silabs.com
| Building a more connected world. Preliminary Rev. 0.5 | 5 Document Outline 1. Ordering Guide 2. System Overview 3. Current Sense Application 4. Electrical Specifications 4.1 Regulatory Information 4.2 Typical Operating Characteristics 5. Pin Descriptions 5.1 Si8921 Pin Descriptions 5.2 Si8922 Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Revision History
3. Current Sense Application
In the driver circuit presented below, the Si8921 is used to amplify the voltage across the sense resistor, RSENSE, and transmit the analog signal to the low-voltage domain across an isolation barrier. Isolation is needed because the voltage of RSENSE with respect to ground will swing between 0 V and the high voltage rail connected to the drain of Q1. Floating Low Side High Gate Driver 3.3 to 5V Gate Driver Voltage Bus 24V Supply Supply Supply VDDA PWM Q1 C5 VOA 0.1uF GNDA VDDI GNDI DISABLE R6 VDDB DT VOB GNDB VDDI R3 Si8234 Q3 1.82K To Controller C3 D1 C2 C4 0.1uF 5.6V 0.1uF 0.1uF 1 VDDA VDDB 8 RSENSE R1 20 2 R4 AIP AOP 7 + C1 3 AIN AON 6 C6 ADC 10nF 4 R2 20 GNDA GNDB 5 R5 _ Load Si8921 Q2
Figure 3.1. Current Sense Application
The load in this application can be a motor winding or a similar inductive winding. In a three-phase motor drive application, this circuit would be repeated three times, one for each phase. RSENSE should be a small resistor value to reduce power loss. However, an ex- cessively low resistance will reduce the signal-to-noise ratio of the measurement. Si8921/22 offers two specified full-scale input options, ±62.5 mV (Si8921A/22A) and ±250 mV (Si8921B/22B), for optimizing the value of RSENSE. AIP and AIN connections to the RSENSE resistor should be made as close as possible to each end of the RSENSE resistor as trace resistance will add error to the measurement. The input to the Si8921/22 is differential, and the PCB traces back to the input pins should run in parallel. This ensures that any large noise transients that occur on the high-voltage side are coupled equally to the AIP and AIN pins and will be rejected by the Si8921/22 as a common-mode signal. The amplifier bandwidth of the Si8921/22 is approximately 600 kHz. If further input filtering is required, a passive, differential RC low- pass filter can be placed between RSENSE and the input pins. Values of R1 = R2 = 20 Ω and C1 = 10 nF, as shown in Figure 3.1 Current Sense Application on page 5, provides a cutoff at approximately 400 kHz. For the lowest gain error, R1 and R2 should always be less than 33 Ω to keep the source impedance sufficiently low compared to the Si8921/22 input impedance. The common-mode voltage of AIN and AIP must be greater than –0.2 V but less than 1 V with respect to GNDA. To meet this require- ment, connect GNDA of the Si8921/22 to one side of the RSENSE resistor. In this example, GNDA, RSENSE, the source of Q1, and the drain of Q2 are connected. The ground of the gate driver (Silicon Labs’ Si8234 in this circuit) is also commonly connected to the same node. The Q1 gate driver has a floating supply, 24 V in this example. Since the input and output of the Si8921/22 are galvanically isolated from each other, separate power supplies are necessary on each side. Q3, R3, C3, and D1 make a regulator circuit for powering the input side of the Si8921/22 from this floating supply. D1 establishes a voltage of 5.6 V at the base of Q3. R3 is selected to provide a Zener current of 10 mA for D1. C3 provides filtering at the base of Q3, and the emitter output of Q3 provides approximately 5 V to VDDA. C2 is a bypass capacitor for the supply and should be placed at the VDDA pin with its return trace connecting to the GNDA connection at RSENSE. C4, the local bypass capacitor for the B-side of Si8921/22, should be placed closed to VDDB supply pin with its return close to GNDB. The output signal at AOP and AON is differential with a nominal gain of 8.2 (Si8921B) or 34.8 (Si8921A) and common mode of 1.4 V. The outputs are sampled by a differential input ADC. Depending on the sample rate of the ADC, an anti-aliasing filter may be required. A simple anti-aliasing filter can be made from the passive components, R4, C6, and R5. The characteristics of this filter are dictated by the input topology and sampling frequency of the ADC. However, to ensure the Si8921 outputs are not overloaded, R4 = R5 > 5 kΩ and C6 can be calculated by the following equation: 1 C6 = 2 × π × (R4 + R5) × f3dB
silabs.com
| Building a more connected world. Preliminary Rev. 0.5 | 5 Document Outline 1. Ordering Guide 2. System Overview 3. Current Sense Application 4. Electrical Specifications 4.1 Regulatory Information 4.2 Typical Operating Characteristics 5. Pin Descriptions 5.1 Si8921 Pin Descriptions 5.2 Si8922 Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Revision History