Datasheet Si8935/36/37 (Silicon Labs) - 4
| 制造商 | Silicon Labs |
| 描述 | Delta-Sigma Modulator for Voltage Measurement |
| 页数 / 页 | 25 / 4 — 2. System Overview. Transmitter. Receiver. Figure 2.1. Si8935/36/37 … |
| 修订版 | 0.1 |
| 文件格式/大小 | PDF / 471 Kb |
| 文件语言 | 英语 |
2. System Overview. Transmitter. Receiver. Figure 2.1. Si8935/36/37 Functional Block Diagram. silabs.com
该数据表的模型线
文件文字版本
Si8935/36/37 Data Sheet System Overview
2. System Overview
The input to the Si8935/36/37 is designed for 0 to 2.5 V nominal input. The analog input stage of the Si8935/36/37 is a single-ended amplifier feeding the input of a second-order, delta-sigma (ΔΣ) modulator that digitizes the input signal into a 1-bit output stream. The isolated data output ADAT pin of the converter provides a stream of digital ones and zeros that is synchronous to the ACLK pin. The Si8936/37 clock is generated internally while the Si8935 clock is provided externally. The time average of this serial bit-stream output is proportional to the analog input voltage. The Si8935/36/37 implements a fail-safe output when the high-side supply voltage VDDA goes away. The fail-safe output is steady state logic 0 on ADAT for the externally clocked Si8935. The fail-safe output is a steady state logic 1 on ADAT for the internally clocked Si8936/37. The clock output ACLK of the Si8946/47 will stop after 256 cycles with a steady state logic 1. When the supply comes back, the clock will be turned back on and normal DSM data stream will be output in approximately 200 μs. To differentiate from the fail-safe output, a full-scale input signal will generate a single one or zero every 128 bits at ADAT, depending on the actual polarity of the signal being sensed. When a loss of VDDA supply occurs the part will automatically move into a lower power mode that reduces IDDB current to approxi- mately 1 mA. Similarly, a loss of VDDB supply will reduce IDDA current to approximately 1 mA. When the supply voltage is returned, normal operation begins in approximately 250 μs. Si8935, Si8936, Si8937 VDDA VDDB VIN CLK ACLK DSM NC ADAT
Transmitter Receiver
GNDA CMOS Isolation GNDB
Figure 2.1. Si8935/36/37 Functional Block Diagram silabs.com
| Building a more connected world. Preliminary Rev. 0.1 | 4 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Voltage Sense Application 4. Electrical Specifications 4.1 Regulatory Information 5. Pin Descriptions 5.1 Si8935/36/37 Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Document Revision History
2. System Overview
The input to the Si8935/36/37 is designed for 0 to 2.5 V nominal input. The analog input stage of the Si8935/36/37 is a single-ended amplifier feeding the input of a second-order, delta-sigma (ΔΣ) modulator that digitizes the input signal into a 1-bit output stream. The isolated data output ADAT pin of the converter provides a stream of digital ones and zeros that is synchronous to the ACLK pin. The Si8936/37 clock is generated internally while the Si8935 clock is provided externally. The time average of this serial bit-stream output is proportional to the analog input voltage. The Si8935/36/37 implements a fail-safe output when the high-side supply voltage VDDA goes away. The fail-safe output is steady state logic 0 on ADAT for the externally clocked Si8935. The fail-safe output is a steady state logic 1 on ADAT for the internally clocked Si8936/37. The clock output ACLK of the Si8946/47 will stop after 256 cycles with a steady state logic 1. When the supply comes back, the clock will be turned back on and normal DSM data stream will be output in approximately 200 μs. To differentiate from the fail-safe output, a full-scale input signal will generate a single one or zero every 128 bits at ADAT, depending on the actual polarity of the signal being sensed. When a loss of VDDA supply occurs the part will automatically move into a lower power mode that reduces IDDB current to approxi- mately 1 mA. Similarly, a loss of VDDB supply will reduce IDDA current to approximately 1 mA. When the supply voltage is returned, normal operation begins in approximately 250 μs. Si8935, Si8936, Si8937 VDDA VDDB VIN CLK ACLK DSM NC ADAT
Transmitter Receiver
GNDA CMOS Isolation GNDB
Figure 2.1. Si8935/36/37 Functional Block Diagram silabs.com
| Building a more connected world. Preliminary Rev. 0.1 | 4 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Voltage Sense Application 4. Electrical Specifications 4.1 Regulatory Information 5. Pin Descriptions 5.1 Si8935/36/37 Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Document Revision History