Datasheet Si8935/36/37 (Silicon Labs) - 6
| 制造商 | Silicon Labs |
| 描述 | Delta-Sigma Modulator for Voltage Measurement |
| 页数 / 页 | 25 / 6 — 3. Voltage Sense Application. Figure 3.1. Voltage Sense Application. … |
| 修订版 | 0.1 |
| 文件格式/大小 | PDF / 471 Kb |
| 文件语言 | 英语 |
3. Voltage Sense Application. Figure 3.1. Voltage Sense Application. silabs.com
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Si8935/36/37 Data Sheet Voltage Sense Application
3. Voltage Sense Application
A typical isolated voltage sensing application circuit is shown below. In this example, a high voltage is divided down to produce a volt- age (VIN) within the optimum input signal range of the Si8935/36/37. Numerous alternative inputs configurations are possible with the flexibility of a high impedance input isolator. The Si8935/36/37 senses the single-ended input voltage where it is oversampled and con- verted into a 1-bit bitstream, then transmitted across the isolation barrier to be processed by the system controller/FPGA. If the voltage sensed is > 2.5 V, a simple voltage divider consisting of R1 and R2 can be used to scale down any voltage to fit the input range of the Si8935/36/37. R2 < 10 kΩ is recommended for best performance. 3 to 5.5V 3 to 5.5V Supply Supply C2 C4 R1 0.1uF 0.1uF 1 8 FPGA VDDA VDDB 2 7 VIN ACLK SINC3 3 6 C1 R2 ≤ 10KΩ NC ADAT 4 5 GNDA GNDB Clock Si8935/36/37
Figure 3.1. Voltage Sense Application
The Si8935/36/37 has intrinsic low-pass filtering at approximately 800 kHz. For applications where input filtering is required, a passive, differential RC low-pass filter can be placed at the input pin. Consider the source resistance of the signal measured (or the parallel combination of R1 and R2 if using a voltage divider) as it should be included in the filter calculation. Capacitor C1 should be sized to make a band limiting filter at the desired frequency. C4, the local bypass capacitor for the B-side of Si8935/36/37, should be placed closed to VDDB supply pin with its return close to GNDB. The output signal typically goes directly to a digital filter for additional processing. The digital filter may be implemented by a dedicated FPGA in the system or may be a peripheral in the main system controller. The Si8935 expects an external clock to provide the clock signal for the modulator. That external clock can be provided by the same device that implements the digital filtering or anoth- er device that syncs both the modulator and the digital filter. The Si8936/37 generates an internal clock to the digital filter.
silabs.com
| Building a more connected world. Preliminary Rev. 0.1 | 6 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Voltage Sense Application 4. Electrical Specifications 4.1 Regulatory Information 5. Pin Descriptions 5.1 Si8935/36/37 Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Document Revision History
3. Voltage Sense Application
A typical isolated voltage sensing application circuit is shown below. In this example, a high voltage is divided down to produce a volt- age (VIN) within the optimum input signal range of the Si8935/36/37. Numerous alternative inputs configurations are possible with the flexibility of a high impedance input isolator. The Si8935/36/37 senses the single-ended input voltage where it is oversampled and con- verted into a 1-bit bitstream, then transmitted across the isolation barrier to be processed by the system controller/FPGA. If the voltage sensed is > 2.5 V, a simple voltage divider consisting of R1 and R2 can be used to scale down any voltage to fit the input range of the Si8935/36/37. R2 < 10 kΩ is recommended for best performance. 3 to 5.5V 3 to 5.5V Supply Supply C2 C4 R1 0.1uF 0.1uF 1 8 FPGA VDDA VDDB 2 7 VIN ACLK SINC3 3 6 C1 R2 ≤ 10KΩ NC ADAT 4 5 GNDA GNDB Clock Si8935/36/37
Figure 3.1. Voltage Sense Application
The Si8935/36/37 has intrinsic low-pass filtering at approximately 800 kHz. For applications where input filtering is required, a passive, differential RC low-pass filter can be placed at the input pin. Consider the source resistance of the signal measured (or the parallel combination of R1 and R2 if using a voltage divider) as it should be included in the filter calculation. Capacitor C1 should be sized to make a band limiting filter at the desired frequency. C4, the local bypass capacitor for the B-side of Si8935/36/37, should be placed closed to VDDB supply pin with its return close to GNDB. The output signal typically goes directly to a digital filter for additional processing. The digital filter may be implemented by a dedicated FPGA in the system or may be a peripheral in the main system controller. The Si8935 expects an external clock to provide the clock signal for the modulator. That external clock can be provided by the same device that implements the digital filtering or anoth- er device that syncs both the modulator and the digital filter. The Si8936/37 generates an internal clock to the digital filter.
silabs.com
| Building a more connected world. Preliminary Rev. 0.1 | 6 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Voltage Sense Application 4. Electrical Specifications 4.1 Regulatory Information 5. Pin Descriptions 5.1 Si8935/36/37 Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Document Revision History