Datasheet AS6500 (AustriaMicroSystems) - 10

Document Feedback AS6500 Recommended Operation Conditions
5 Recommended Operation Conditions
Recommended operating ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Test conditions for guaranteed specification are expressly denoted.
Figure 6: Recommended Operation Conditions of AS6500 Symbol Pin Description Min Typ Max Unit Power-Supply
DVDD33, VDD33 TVDD33, Supply Voltage 2.4 3.3 3.6 V RVDD33 DVDD18, Core Supply Voltage VDD18 TVDD18, powered by integrated 1.7 1.8 1.9 V CVDD18 regulator, pin VDD18O
Temperature
Operating free air TA -40 125 °C temperature(1)
Reference & Stop Inputs
VIL,CMOS STOP1, STOP2, CMOS Input Low Voltage 0.4 V STOP3, STOP4, VIH,CMOS REFCLK, VDD33 RSTIDX, CMOS Input High Voltage – V 0.4 DISBALE
SPI-Interface
VIL Digital Input LOW Voltage 0.8 V SCK, MOSI, SSN 0.7 × VIH Digital Input HIGH Voltage V VDD33 INTERRUPT, Load Capacitance to CLOAD 20 pF MISO Ground (1) Recommended Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Test conditions for guaranteed specification are explicitly denoted. Datasheet • PUBLIC DS000640 • v3-00 • 2019-Feb-21 56 │ 10 Document Outline Content Guide 1 General Description 1.1 Key Benefits & Features 1.2 Applications 1.3 Block Diagram 2 Ordering Information 3 Pin Assignment 3.1 Pin Diagram 3.2 Pin Description 4 Absolute Maximum Ratings 5 Recommended Operation Conditions 6 Typical Characteristics 6.1 Converter Characteristics 6.2 Power Supply Characteristics 6.3 Reference Clock and Stop Input Requirements 6.4 Serial Communication Interface 6.5 Typical Operating Characteristics 7 Register Description 7.1 Register Overview 7.2 Detailed Register Description 7.2.1 CFG0 Register (Address 0) 7.2.2 CFG1 Register (Address 1) 7.2.3 CFG2 Register (Address 2) 7.2.4 CFG3, CFG4, CFG5 Registers (Addresses 3 to 5) 7.2.5 CFG6 Register (Address 6) 7.2.6 CFG7 Register (Address 7) 7.2.7 CFG8 to CFG15 Register (Addresses 8 to 15) 7.2.8 CFG16 Register (Address 16) 7.2.9 CHANNEL1 Result Register (Addresses 8 to 13) 7.2.10 CHANNEL2 Result Register (Addresses 14 to 19) 7.2.11 CHANNEL3 Result Register (Addresses 20 to 25) 7.2.12 CHANNEL4 Result Register (Addresses 26 to 31) 8 Detailed Description 8.1 Time Measurements and Results 8.1.1 Measurements of AS6500 8.1.2 Output Results 8.1.3 Calculation of Time Differences GENERAL APPROACH 8.2 Resolution 8.2.1 RMS-Resolution versus Effective Resolution 8.2.2 High Resolution 8.3 Combining Two Stop Channels 8.3.1 Channel Combination for Low Pulse-to-Pulse Spacing 8.3.2 Channel Combination for Pulse Width Measurement 8.4 Input Pins for Time Measurement 8.4.1 REFCLK: Reference Clock Input 8.4.2 RSTIDX: Reference Index Counter Reset 8.4.3 STOP1 to STOP4: Stop Channels 8.4.4 DISABLE: Stop Disable SOFTWARE ENABLE (HIT_ENA_STOP1…4) PIN ENABLE (PIN_ENA_XXX) 8.5 SPI Communication Interface 8.5.1 General 8.5.2 Detailed Pin Description 8.5.3 Communication Commands (Opcodes) 8.5.4 Data Readout via SPI Interface 8.6 Coding of Results 8.6.1 Configuration of LSB by REFCLK_DIVISIONS 8.6.2 Examples for Codes of Time Measurements Results 8.6.3 Maximum Time Differences 8.7 Conversion Latency and Conversion Rate Converter Latency 8.8 Conversion Rate 8.8.1 Peak Conversion Rate 8.8.2 Read-Out Rate 8.8.3 Average Conversion Rate 8.8.4 FIFOs for Adapting Peak and Average Conversion Rate 9 Application Information 9.1 Configuration Examples 9.2 Example C++ Code 9.3 Schematic 9.4 External Components 10 Package Drawings & Markings 11 Reel Information 12 Soldering & Storage Information 13 Revision Information 14 Legal Information