Datasheet TDC-GPX2 (AustriaMicroSystems) - 6

TDC-GPX2 −
Pin Assignments
Pin No. Pin Name Description Type Not Used
29 CVDD18 1.8V positive supply for TDC Power Supply 30, 51 TVDD18 1.8V positive supply for time front-end Power Supply 31, 37, 50 TGND Ground for 1.8V time front-end supply Power Supply 32, 44, 49 TVDD33 3.3V positive supply for time front-end Power Supply 33 STOP4P Positive stop input for channel 4 CMOS/LVDS Input TVDD33 34 STOP4N Negative stop input for channel 4 LVDS Input TVDD33 35 STOP3P Positive stop input for channel 3 CMOS/LVDS Input TVDD33 36 STOP3N Negative stop input for channel 3 LVDS Input TVDD33 38 DISABLEP Positive disabling pin for stop channels CMOS/LVDS Input TVDD33 39 DISABLEN Negative disabling pin for stop channels LVDS Input TVDD33 40 REFCLKP Positive clock signal of reference clock CMOS/LVDS Input TVDD33 41 REFCLKN Negative clock signal of reference clock LVDS Input TVDD33 42 RSTIDXP Positive reference index reset signal CMOS/LVDS Input TVDD33 43 RSTIDXN Negative reference index reset signal LVDS Input TVDD33 45 STOP2P Positive stop input for channel 2 CMOS/LVDS Input TVDD33 46 STOP2N Negative stop input for channel 2 LVDS Input TVDD33 47 STOP1P Positive stop input for channel 1 CMOS/LVDS Input TVDD33 48 STOP1N Negative stop input for channel 1 LVDS Input TVDD33 52 REFOSCI Input for quartz as reference clock XOSC Driver In Open 53 REFOSCO Output for quartz as reference clock XOSC Driver Out Open 54 PARITY Parity of all configuration registers LVTTL Output Open 55 INTERRUPT SPI interrupt LVTTL Output Open 56 SSN SPI slave select not + interface reset LVTTL Input 57 SCK SPI serial clock LVTTL Input 58 MOSI SPI serial data master out, slave In LVTTL Input 59 MISO SPI serial data master in, slave Out LVTTL Tristate 63 LCLKINP Positive serial clock in LVDS Input DVDD33 64 LCLKINN Negative serial clock in LVDS Input DVDD33
Note(s):
1. A small dot on the package indicates the pin 1. There is no need to connect the exposed pad to GND (internally not connected). Connecting it may be helpful for heat dissipation. The package is RoHS compliant and does not contain any Pb.
Page 6 ams Datasheet
Document Feedback [v1-03] 2017-Dec-18 Document Outline General Description Key Benefits & Features Applications Block Diagram Pin Assignments Pin Diagram Pin Description Absolute Maximum Ratings Recommended Operation Conditions Converter Characteristics Power Supply Characteristic Reference Clock and Stop Input Requirements LVDS Data Interface Characteristics Serial Communication Interface Typical Operating Characteristics Histograms Integral Non-Linearity Register Description Configuration Register Overview Detailed Configuration Register Description Read Register Overview Detailed Description Time Measurements and Results Measurements of TDC-GPX2 Output Results Calculation of Time Differences Resolution RMS-Resolution Versus Effective Resolution High Resolution Combining Two Stop Channels Channel Combination for Low Pulse-to-Pulse Spacing Channel Combination for Pulse Width Measurement Input Pins for Time Measurement REFCLKP/N: Reference Clock Input REFOSCI/O: Quartz Driver as Reference Clock RSTIDXP/N: Reference Index Counter Reset STOP1…STOP4P/N: Stop Channels DISABLE/N: Stop Disable Input Levels, CMOS or LVDS LVDS Output Interface Digital Output Interface Output Setup and Configuration: LVDS Output Buffers Differential LCLKIN Input LVDS Single Data Read Output Interface (SDR) LVDS Double Data Read Output Interface (DDR) LVDS Output Test Pattern SPI Communication Interface General Detailed Pin Description Communication Commands (Opcodes) Detailed Command Description Initialization Reset Write / Incremental Write Read / Incremental Read Using SPI Interface for Read-Out of Stop Results Coding of Results Configuration of LSB by REFCLK_DIVISIONS Examples for Codes of Time Measurements Results Maximum Time Differences Conversion Latency and Conversion Rate Converter Latency LVDS Synchronization Latency Conversion Rate Peak Conversion Rate Read-Out Rate Average Conversion Rate Examples for Read-Out Rate with LVDS FIFOs for Adapting Peak and Average Conversion Rate Application Information Configuration Examples Typical Configuration for LVDS Example C++ Code Schematic External Components PCB Layout Package Drawings & Markings Mechanical Data QFN64 QFN64 Tray Information QFP64 QFP64 Tape & Reel Information Soldering & Storage Information Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information Content Guide