Datasheet ADL5570 (Analog Devices) - 8

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ADL5570 APPLICATIONS BASIC CONNECTIONS RF Output Interface
Figure 10 shows the basic connections for the ADL5570. The parallel RF output ports have a shunt capacitance, C3 (3.3 pF), and the line inductance of the microstrip-line for optimized
VPOS STBY
output power and linearity. The characteristics of the ADL5570
L1 C6 C11
are described for 50 Ω impedance after the output matching
1nH 3.6pF 1µF C8
capacitor (load after C3).
VPOS 0.01µF VPOS1 VPOS1 C7 4 3 2 1 L2 C5 C12 0.01µF Y D 2 C 11nH OPEN 1µF B N C N L2 T C5 C12 G C S V 11pF OPEN 1µF 5 VCC1 NC 16 RFIN L3 C4 RFOUT 6 RFIN RFOUT 15 2.7nH ADL5570 39pF C4 C3 39pF 7 GND RFOUT 14 3.3pF RFOUT 15 RFOUT 8 VREG E VREG NC 13 T D RFOUT 14 C9 L O C C 0.01µF F M N N C3 C
5
9 01 11 21 3.3pF
-00 29 067
C2 2.2pF
Figure 12. RF Output
VPOS1 W1 VPOS R1
C4 provides dc blocking on the RF output.
50kΩ MODE Transmit/Standby Enable C10 0.01µF
03 0 During normal transmit mode, the STBY pin is biased low 9- 72
NC = NO CONNECT
06 (0 V). However, during receive mode, the pin can be biased Figure 10. ADL5570 Basic Connections high (2.5 V) to shift the device into standby mode, which
Power Supply
reduces current consumption to less than 1 mA. The voltage supply on the ADL5570, which ranges from
VREG Enable
3.2 V to 4.2 V, should be connected to the VCCx pins. VCC1 is During normal transmit, the VREG pin is biased to 2.85 V and decoupled with Capacitor C7, whereas VCC2 uses a tank circuit draws 10 mA of current. When the VREG pin is low (0 V), the to prevent RF signals from propagating on the dc lines. device suspends itself into sleep mode (irrespective of supply
RF Input Interface
and MODE biasing). In this mode, the device draws 10 μA of The RFIN pin is the port for the RF input signal to the current. power amplifier. The L3 inductor, 2.7 nH, matches the input
MODE High Power/Low Power Enable
impedance to 50 Ω. The MODE pin is used to choose between high power mode
2.7nH
and low power mode. When MODE is biased low (0 V), the
6 RFIN
040
L3
9- device operates in high power mode. When MODE is biased 672 0 high (2.5 V), the device operates in low power mode. Appropriate Figure 11. RF Input with Matching Component biasing must be followed for 3.5 V and 4.2 V operation. See Table 4 and Table 5 for configuration of the MODE pin. Rev. 0 | Page 8 of 12 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS VCC = 3.5 V ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS BASIC CONNECTIONS Power Supply RF Input Interface RF Output Interface Transmit/Standby Enable VREG Enable MODE High Power/Low Power Enable 64 QAM OFDMA PERFORMANCE POWER-ADDED EFFICIENCY EVALUATION BOARD MEASUREMENT SETUP USING THE ADL5570 EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE