Datasheet 2N5551 / MMBT5551 (ON Semiconductor) - 9
| 制造商 | ON Semiconductor |
| 描述 | NPN General Purpose Amplifier |
| 页数 / 页 | 11 / 9 — 2 N 5551 / MMBT5551 — NPN Ge. Physical Dimensions. neral-Purpose Amplifier |
| 修订版 | 2 |
| 文件格式/大小 | PDF / 417 Kb |
| 文件语言 | 英语 |
2 N 5551 / MMBT5551 — NPN Ge. Physical Dimensions. neral-Purpose Amplifier
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2 N 5551 / MMBT5551 — NPN Ge Physical Dimensions
(Continued) SOT-23 2.92±0.20 0.95 3 1.40 1.30+0.20 2.20
neral-Purpose Amplifier
-0.15 1 2 (0.29) 0.60 0.37 0.95 0.20 A B 1.00 1.90 1.90 LAND PATTERN RECOMMENDATION 1.20 MAX SEE DETAIL A (0.93) 0.10 0.00 0.10 C C 2.40±0.30 NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE A) REFERENCE JEDEC REGISTRATION TO-236, VARIATION AB, ISSUE H. B) ALL DIMENSIONS ARE IN MILLIMETERS. 0.23 0.08 C) DIMENSIONS ARE INCLUSIVE OF BURRS, 0.25 MOLD FLASH AND TIE BAR EXTRUSIONS. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 0.20 MIN SEATING E) DRAWING FILE NAME: MA03DREV10 (0.55) PLANE SCALE: 2X
Figure 12. 3-LEAD, SOT23, JEDEC TO-236, LOW PROFILE (ACTIVE)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packaging/tr/SOT23-3L_tr.pdf. © 2009 Semiconductor Components Industries, LLC www.onsemi.com 2N5551 / MMBT5551 Rev. 2 8
(Continued) SOT-23 2.92±0.20 0.95 3 1.40 1.30+0.20 2.20
neral-Purpose Amplifier
-0.15 1 2 (0.29) 0.60 0.37 0.95 0.20 A B 1.00 1.90 1.90 LAND PATTERN RECOMMENDATION 1.20 MAX SEE DETAIL A (0.93) 0.10 0.00 0.10 C C 2.40±0.30 NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE A) REFERENCE JEDEC REGISTRATION TO-236, VARIATION AB, ISSUE H. B) ALL DIMENSIONS ARE IN MILLIMETERS. 0.23 0.08 C) DIMENSIONS ARE INCLUSIVE OF BURRS, 0.25 MOLD FLASH AND TIE BAR EXTRUSIONS. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 0.20 MIN SEATING E) DRAWING FILE NAME: MA03DREV10 (0.55) PLANE SCALE: 2X
Figure 12. 3-LEAD, SOT23, JEDEC TO-236, LOW PROFILE (ACTIVE)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packaging/tr/SOT23-3L_tr.pdf. © 2009 Semiconductor Components Industries, LLC www.onsemi.com 2N5551 / MMBT5551 Rev. 2 8