Datasheet TMPM4G Group(1) (Toshiba)
| 制造商 | Toshiba |
| 描述 | TXZ4 |
| 页数 / 页 | 132 / 1 — TMPM4G Group(1). Datasheet. General Description. Applications. Features |
| 文件格式/大小 | PDF / 1.7 Mb |
| 文件语言 | 英语 |
TMPM4G Group(1). Datasheet. General Description. Applications. Features
该数据表的模型线
TMPM4G
文件文字版本
TMPM4G Group(1) Datasheet
CMOS Digital Integrated Circuit Silicon Monolithic LQFP176(20x20mm, 0.4mm pitch)
TMPM4G Group(1)
LQFP144(20x20mm, 0.5mm pitch) LQFP128(14x14mm, 0.4mm pitch) LQFP100(14x14mm, 0.5mm pitch)
General Description
VFBGA177(13x13mm, 0.8mm pitch) ● VFBGA145(12x12mm, 0.8mm pitch) Arm ® Cortex®-M4( with FPU) ● Frequency: 1 to 160 MHz, Operation voltage: 2.7 to 3.6 V ● Code Flash: 512 KB to 1536 KB. Data Flash: 32KB ● Built-in High speed 12-bit AD converter and plenty of timers/serial channels
Applications
TMPM4G group(1) integrates widely used for the equipment in which high speed data procedure is required, such as OA/digital products, industrial equipment, and others.
Features
● Arm Cortex-M4( with FPU) ‒ Operation frequency: 1 to 160 MHz ● I/O ports: 87 to 155 (Input: 4, Output: 1) ‒ Memory Protection Unit (MPU) ‒ Enable to select Pull-up/Pull-down resistor, Open-drain ● Supply voltage and power consumption ‒ 5V tolerant, 3V tolerant ‒ Operation voltage: 2.7 to 3.6 V ● On-chip debug (JTAG/SW) and NBDIF (RAM monitor) ‒ Low-power consumption operation: IDLE, STOP1, and STOP2 ● Trigger Selector (TRGSEL) ● Operation temperature: ‒ Expand trigger requests for DMA Controller, Timer counter, and - 40 to +85℃@operation frequency 1 to 120 MHz others. - 40 to +70℃@operation frequency 1 to 160 MHz ● DMA Controller: 3 units ● Internal memory ‒ MDMAC: 1 unit, ‒ Code Flash: 512 KB to 1536 KB, rewritable up to 10,000 times DMA requests: 30 to 32 factors, internal/external triggers ‒ Data Flash: 32 KB, rewritable up to 100,000 times ‒ HDMAC: 2 units, ‒ Data Flash is rewritable during instruction execution DMA requests: 13 to 15 factors, internal/external triggers ‒ RAM: 128 KB to 192 KB and Backup RAM: 2 KB (all products) ● External bus interface(EBIF) ● Clock ‒ Expandable to 64MB(Program/data) ‒ External high speed oscil ator: 8 MHz to 20 MHz (Ceramic and ‒ External data bus(separate bug/multiplexed bun): 8/16 bit width Crystal) ‒ Chip select controller: 4 channels ‒ External high speed clock input: 8 to 20 MHz ● Asynchronous serial communication ‒ Internal high speed oscil ator1 (IHOSC1):10MHz, user trimming ‒ UART: 3 to 6 channels, 5.0 Mbps (Max). FIFO (Transmission function 8 stage and Reception 8 stage) ‒ Internal high speed oscil ator2 (IHOSC2):10MHz ‒ FUART: 1 or 2 channels, 2.5Mbps (Max). FIFO (Transmission ‒ PLL: 160 MHz output 32 stage and Reception 32 stage) and IrDA 115.2Kbps (Max). ‒ External low speed oscil ator: 32.768 kHz ● Serial Peripheral Interface (TSPI): 5 to 9 channels ● Oscil ation Frequency Detectior (OFD): Abnormal system clock ‒ SIO/SPI mode, 25 Mbps (Max) detection ‒ FIFO (Transmission 16bit x 8 stage and Reception 16bit x 8 ● Voltage Detection (LVD): 7 levels. selection between interrupts stage) and reset outputs ● I2C Interface (I2C): 3 to 5 channels ● Interrupt Multi master, standard mode/fast mode available ‒ External: 12 to 16 factors. Integrate digital noise filters (DNF). ● Serial Memory Interface (SMIF): 1 channel ‒ Internal: 91 to 124 factors ‒ Connectable to two SPI FLASH 2018-11-12 1 / 132 Rev.4.1 © 2018 Toshiba Electronic Devices & Storage Corporation Document Outline General Description Applications Features Products Lists Categorized by Functions 1. Block Diagram 2. Pin Assignment 2.1. LQFP176 2.2. LQFP144 2.3. LQFP128 2.4. LQFP100 2.5. VFBGA177 2.6. VFBGA145 3. Memory Map 3.1. List of Memory Sizes 4. Pin Description 4.1. Functional Pin Name and Function 4.1.1. Peripheral Function Pins 4.1.2. Debug Pins 4.1.3. Control Pins 4.1.4. Power Supply Pins 4.2. Functional Pin and Port Assignment (Pin Number) 4.3. Ports 4.3.1. Port Specifications Table 5. Functional Description and Operation Description 5.1. Reference Manuals 5.2. Processor Core 5.2.1. Core Information 5.2.2. Configurable Options 5.3. Clock Control and Operation Mode (CG) 5.4. Flash Memory (Code FLASH, Data FLASH) 5.5. Oscillation Circuit 5.6. Trimming Circuit (TRM) 5.7. Oscillation Frequency Detector (OFD) 5.8. Voltage Detection Circuit (LVD) 5.9. Digital Noise Filter Circuit (DNF) 5.10. Debug Interface (DEBUG) 5.11. Non Break Debug Interface(NBDIF) 5.12. Interval Sensor Detection Circuit(ISD) 5.13. DMA Controller 5.13.1. Multi-Function DMA Controller (MDMAC) 5.13.2. High Speed DMA Controller (HDMAC) 5.14. External Bus Interface (EBIF) 5.15. Serial Memory Interface (SMIF) 5.16. Asynchronous Serial Communication Circuit 5.16.1. Asynchronous Serial Communication Circuit (UART) 5.16.2. Full Universal Asynchronous Receiver Transmitter Circuit (FUART) 5.17. Serial Peripheral Interface (TSPI) 5.18. I2C Interface (I2C) 5.19. Consumer Electronics Control Circuit (CEC) 5.20. 8-bit Digital to Analog Converter (DAC) 5.21. 12-bit Analog to Digital Converter (ADC) 5.22. Advanced Programmable Motor Control Circuit (A-PMD) 5.23. 32-bit Timer Event Counter (T32A) 5.24. Long Term Timer (LTTMR) 5.25. Real Time Clock (RTC) 5.26. Clock Selective Watchdog Timer (SIWDT) 5.27. Remote Control Signal Preprocessor (RMC) 5.28. Boundary-scan (BSC) 6. Equivalent Circuit 6.1. Port 6.2. Analog Power pin 6.3. Control Pin 6.4. Clock control 7. Electrical Characteristics 7.1. Absolute Maximum Ratings 7.2. DC Electrical Characteristics (1/2) 7.3. DC Electrical Characteristics (2/2) (Consumption current) 7.4. 12-bit AD Converter Characteristics 7.5. 8-bit DA Converter Characteristics 7.6. Characteristics of Internal processing at RESET 7.7. Characteristics of Power on Reset 7.8. Characteristics of Voltage Detection Circuit 7.9. AC Electrical Characteristics 7.9.1. Serial Peripheral Interface (TSPI) 7.9.1.1. AC Measurement Conditions 7.9.1.2. AC Electrical Characteristics 7.9.2. I2C Interface (I2C) 7.9.3. 32-bit Timer Event Counter (T32A) 7.9.4. External Bus Interface(EBIF) 7.9.4.3. AC Electrical Characteristics (EEXBCLK asynchronous Separate Mode) 7.9.4.4. AC Electrical Characteristics (EEXBCLK asynchronous multiplex bus mode) 7.9.4.5. AC Electrical Characteristics (EEXBCLK synchronous separate bus mode / multiplex bus mode) 7.9.5. Serial Memory Interface (SMIF) 7.9.5.1. AC Measurement Conditions 7.9.6. External Interrupt 7.9.6.1. AC Measurement Conditions 7.9.6.2. AC Electrical Characteristics 7.9.7. Trigger Input (TRGINx) 7.9.7.1. AC Measurement Conditions 7.9.7.2. AC Electrical Characteristics 7.9.8. Debug Communication 7.9.8.1. AC Measurement Conditions 7.9.8.2. SWD Interface 7.9.8.3. JTAG Interface 7.9.8.4. ETM Trace 7.9.8.6. Noise Filter Characteristics 7.9.9. External Clock Input 7.9.9.1. AC Measurement Conditions 7.10. Flash Memory Characteristics 7.10.1. Code Flash 7.10.2. Data Flash 7.10.3. Chip Erase 7.11. Regulator 7.12. Oscillation Circuit 7.12.1. Internal Oscillator 7.12.2. External Oscillator 7.12.3. Ceramic Oscillator 7.12.4. Crystal Oscillator 7.12.5. Precautions for designing printed circuit board 8. Package Dimensions 8.1. P-LQFP176-2020-0.40-002 8.2. P-LQFP144-2020-0.50-002 8.3. P-LQFP128-1414-0.40-001 8.4. P-LQFP100-1414-0.50-002 8.5. P-VFBGA177-1313-0.80-001 8.6. P-VFBGA145-1212-0.80-001 9. Precautions 10. Revision History Part Naming Conventions
CMOS Digital Integrated Circuit Silicon Monolithic LQFP176(20x20mm, 0.4mm pitch)
TMPM4G Group(1)
LQFP144(20x20mm, 0.5mm pitch) LQFP128(14x14mm, 0.4mm pitch) LQFP100(14x14mm, 0.5mm pitch)
General Description
VFBGA177(13x13mm, 0.8mm pitch) ● VFBGA145(12x12mm, 0.8mm pitch) Arm ® Cortex®-M4( with FPU) ● Frequency: 1 to 160 MHz, Operation voltage: 2.7 to 3.6 V ● Code Flash: 512 KB to 1536 KB. Data Flash: 32KB ● Built-in High speed 12-bit AD converter and plenty of timers/serial channels
Applications
TMPM4G group(1) integrates widely used for the equipment in which high speed data procedure is required, such as OA/digital products, industrial equipment, and others.
Features
● Arm Cortex-M4( with FPU) ‒ Operation frequency: 1 to 160 MHz ● I/O ports: 87 to 155 (Input: 4, Output: 1) ‒ Memory Protection Unit (MPU) ‒ Enable to select Pull-up/Pull-down resistor, Open-drain ● Supply voltage and power consumption ‒ 5V tolerant, 3V tolerant ‒ Operation voltage: 2.7 to 3.6 V ● On-chip debug (JTAG/SW) and NBDIF (RAM monitor) ‒ Low-power consumption operation: IDLE, STOP1, and STOP2 ● Trigger Selector (TRGSEL) ● Operation temperature: ‒ Expand trigger requests for DMA Controller, Timer counter, and - 40 to +85℃@operation frequency 1 to 120 MHz others. - 40 to +70℃@operation frequency 1 to 160 MHz ● DMA Controller: 3 units ● Internal memory ‒ MDMAC: 1 unit, ‒ Code Flash: 512 KB to 1536 KB, rewritable up to 10,000 times DMA requests: 30 to 32 factors, internal/external triggers ‒ Data Flash: 32 KB, rewritable up to 100,000 times ‒ HDMAC: 2 units, ‒ Data Flash is rewritable during instruction execution DMA requests: 13 to 15 factors, internal/external triggers ‒ RAM: 128 KB to 192 KB and Backup RAM: 2 KB (all products) ● External bus interface(EBIF) ● Clock ‒ Expandable to 64MB(Program/data) ‒ External high speed oscil ator: 8 MHz to 20 MHz (Ceramic and ‒ External data bus(separate bug/multiplexed bun): 8/16 bit width Crystal) ‒ Chip select controller: 4 channels ‒ External high speed clock input: 8 to 20 MHz ● Asynchronous serial communication ‒ Internal high speed oscil ator1 (IHOSC1):10MHz, user trimming ‒ UART: 3 to 6 channels, 5.0 Mbps (Max). FIFO (Transmission function 8 stage and Reception 8 stage) ‒ Internal high speed oscil ator2 (IHOSC2):10MHz ‒ FUART: 1 or 2 channels, 2.5Mbps (Max). FIFO (Transmission ‒ PLL: 160 MHz output 32 stage and Reception 32 stage) and IrDA 115.2Kbps (Max). ‒ External low speed oscil ator: 32.768 kHz ● Serial Peripheral Interface (TSPI): 5 to 9 channels ● Oscil ation Frequency Detectior (OFD): Abnormal system clock ‒ SIO/SPI mode, 25 Mbps (Max) detection ‒ FIFO (Transmission 16bit x 8 stage and Reception 16bit x 8 ● Voltage Detection (LVD): 7 levels. selection between interrupts stage) and reset outputs ● I2C Interface (I2C): 3 to 5 channels ● Interrupt Multi master, standard mode/fast mode available ‒ External: 12 to 16 factors. Integrate digital noise filters (DNF). ● Serial Memory Interface (SMIF): 1 channel ‒ Internal: 91 to 124 factors ‒ Connectable to two SPI FLASH 2018-11-12 1 / 132 Rev.4.1 © 2018 Toshiba Electronic Devices & Storage Corporation Document Outline General Description Applications Features Products Lists Categorized by Functions 1. Block Diagram 2. Pin Assignment 2.1. LQFP176 2.2. LQFP144 2.3. LQFP128 2.4. LQFP100 2.5. VFBGA177 2.6. VFBGA145 3. Memory Map 3.1. List of Memory Sizes 4. Pin Description 4.1. Functional Pin Name and Function 4.1.1. Peripheral Function Pins 4.1.2. Debug Pins 4.1.3. Control Pins 4.1.4. Power Supply Pins 4.2. Functional Pin and Port Assignment (Pin Number) 4.3. Ports 4.3.1. Port Specifications Table 5. Functional Description and Operation Description 5.1. Reference Manuals 5.2. Processor Core 5.2.1. Core Information 5.2.2. Configurable Options 5.3. Clock Control and Operation Mode (CG) 5.4. Flash Memory (Code FLASH, Data FLASH) 5.5. Oscillation Circuit 5.6. Trimming Circuit (TRM) 5.7. Oscillation Frequency Detector (OFD) 5.8. Voltage Detection Circuit (LVD) 5.9. Digital Noise Filter Circuit (DNF) 5.10. Debug Interface (DEBUG) 5.11. Non Break Debug Interface(NBDIF) 5.12. Interval Sensor Detection Circuit(ISD) 5.13. DMA Controller 5.13.1. Multi-Function DMA Controller (MDMAC) 5.13.2. High Speed DMA Controller (HDMAC) 5.14. External Bus Interface (EBIF) 5.15. Serial Memory Interface (SMIF) 5.16. Asynchronous Serial Communication Circuit 5.16.1. Asynchronous Serial Communication Circuit (UART) 5.16.2. Full Universal Asynchronous Receiver Transmitter Circuit (FUART) 5.17. Serial Peripheral Interface (TSPI) 5.18. I2C Interface (I2C) 5.19. Consumer Electronics Control Circuit (CEC) 5.20. 8-bit Digital to Analog Converter (DAC) 5.21. 12-bit Analog to Digital Converter (ADC) 5.22. Advanced Programmable Motor Control Circuit (A-PMD) 5.23. 32-bit Timer Event Counter (T32A) 5.24. Long Term Timer (LTTMR) 5.25. Real Time Clock (RTC) 5.26. Clock Selective Watchdog Timer (SIWDT) 5.27. Remote Control Signal Preprocessor (RMC) 5.28. Boundary-scan (BSC) 6. Equivalent Circuit 6.1. Port 6.2. Analog Power pin 6.3. Control Pin 6.4. Clock control 7. Electrical Characteristics 7.1. Absolute Maximum Ratings 7.2. DC Electrical Characteristics (1/2) 7.3. DC Electrical Characteristics (2/2) (Consumption current) 7.4. 12-bit AD Converter Characteristics 7.5. 8-bit DA Converter Characteristics 7.6. Characteristics of Internal processing at RESET 7.7. Characteristics of Power on Reset 7.8. Characteristics of Voltage Detection Circuit 7.9. AC Electrical Characteristics 7.9.1. Serial Peripheral Interface (TSPI) 7.9.1.1. AC Measurement Conditions 7.9.1.2. AC Electrical Characteristics 7.9.2. I2C Interface (I2C) 7.9.3. 32-bit Timer Event Counter (T32A) 7.9.4. External Bus Interface(EBIF) 7.9.4.3. AC Electrical Characteristics (EEXBCLK asynchronous Separate Mode) 7.9.4.4. AC Electrical Characteristics (EEXBCLK asynchronous multiplex bus mode) 7.9.4.5. AC Electrical Characteristics (EEXBCLK synchronous separate bus mode / multiplex bus mode) 7.9.5. Serial Memory Interface (SMIF) 7.9.5.1. AC Measurement Conditions 7.9.6. External Interrupt 7.9.6.1. AC Measurement Conditions 7.9.6.2. AC Electrical Characteristics 7.9.7. Trigger Input (TRGINx) 7.9.7.1. AC Measurement Conditions 7.9.7.2. AC Electrical Characteristics 7.9.8. Debug Communication 7.9.8.1. AC Measurement Conditions 7.9.8.2. SWD Interface 7.9.8.3. JTAG Interface 7.9.8.4. ETM Trace 7.9.8.6. Noise Filter Characteristics 7.9.9. External Clock Input 7.9.9.1. AC Measurement Conditions 7.10. Flash Memory Characteristics 7.10.1. Code Flash 7.10.2. Data Flash 7.10.3. Chip Erase 7.11. Regulator 7.12. Oscillation Circuit 7.12.1. Internal Oscillator 7.12.2. External Oscillator 7.12.3. Ceramic Oscillator 7.12.4. Crystal Oscillator 7.12.5. Precautions for designing printed circuit board 8. Package Dimensions 8.1. P-LQFP176-2020-0.40-002 8.2. P-LQFP144-2020-0.50-002 8.3. P-LQFP128-1414-0.40-001 8.4. P-LQFP100-1414-0.50-002 8.5. P-VFBGA177-1313-0.80-001 8.6. P-VFBGA145-1212-0.80-001 9. Precautions 10. Revision History Part Naming Conventions