Datasheet L5965 (STMicroelectronics) - 7
制造商 | STMicroelectronics |
描述 | Multiple power management for automotive vision and radar systems |
页数 / 页 | 85 / 7 — L5965. Thermal data. Absolute maximum rating. Operating voltage. Pin … |
文件格式/大小 | PDF / 1.3 Mb |
文件语言 | 英语 |
L5965. Thermal data. Absolute maximum rating. Operating voltage. Pin name. Min. Max. Unit. 3.2. 3.2.1. Thermal resistance
该数据表的模型线
文件文字版本
L5965 Thermal data Absolute maximum rating Operating voltage Pin name Min Max Unit Min Max Unit
VIN3 -0.3 6.5 V -0.3 5.5 V BST3 PH3-0.3 PH3+4.6 V PH3-0.3 PH3+3.6 V PH3 -1 6.5 V -1 5.5 V VREG3_S -0.3 4.6 V -0.5 3.6 V PGND3 -0.3 0.3 V -0.3 0.3 V VIN4 -0.3 6.5 V -0.3 5.5 V BST4 PH4-0.3 PH4+4.6 V PH4-0.3 PH4+3.6 V PH4 -1 6.5 V -1 5.5 V VREG4_S -0.3 4.6 V -0.5 3.6 V PGND4 -0.3 0.3 V -0.3 0.3 V PH5 -0.3 9 V -0.3 8 V VBOOST_S -0.3 13 V -0.3 7.5 V PGND5 -0.3 0.3 V -0.3 0.3 V Debug -0.3 42 V -0.3 20 V COMP1 -0.3 4.6 V -0.3 3.6 V COMP2 -0.3 4.6 V -0.3 3.6 V
3.2 Thermal data 3.2.1 Thermal resistance Table 3. Operation junction temperature Symbol Parameter Board Value unit Unit
Rth j-a-2s 2s 66 °C/W Rth j-a-2s2p Thermal resistance junction-to-ambient 2s2p 32 °C/W Rth j-a-2s2pv 2s2p+vias 26 °C/W Rth j-case Thermal resistance junction-to-case 2.2 °C/W
3.2.2 Thermal warning and protection Table 4. Temperature thresholds Symbol Parameter Test condition Min. Typ. Max. Unit
TSD_TH – 160 175 190 °C Thermal Shutdown TSD_hys Hysteresis 0.5 4 8 °C TOT_THx (x=1-7) – 140 155 170 °C Over temperature warning TOT_hysx (x=1-7) Hysteresis 3 7 11 °C TSD_filter Thermal Filter time – – 16 – µs Tj Junction temperature Tj -40 150 °C Tstg Storage temperature Tstg 150 °C
DS12567
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Rev 2 page 7/85
Document Outline 1 Overview 1.1 Simplified block diagram 1.2 Functional block diagram 2 Pins description 3 Electrical specifications 3.1 Absolute maximum ratings & operating voltage 3.2 Thermal data 3.2.1 Thermal resistance 3.2.2 Thermal warning and protection 3.3 Electrical characteristics 3.3.1 Electrical characteristic curves 4 Functional description 4.1 Programming by OTP 4.2 Voltage regulators and features description 4.2.1 VREG 4.2.2 Pre regulator BUCK1 4.2.3 Pre regulator BUCK2 4.2.4 Post regulator BUCK3 4.2.5 Post regulator BUCK4 4.2.6 BOOST 4.2.7 LDO 4.2.8 VREF 4.2.9 ADC 4.2.10 Wake up pin (WKUP) 4.2.11 Synchronizing pin (SYNC in/out) 4.2.12 Reset and Fault 4.2.13 Configurable watchdog and reset 4.2.14 Under-Voltage, Over-Voltage and Power-Good 4.2.15 Temperature control and VBATx voltage through internal ADC 4.2.16 Maximum Duty Cycle and Refresh Mode for Buck 4.2.17 Frequency-Hopping Spread Spectrum 5 SPI format and register mapping 5.1 SPI frame CRC generator 5.2 SPI registers mapping 5.2.1 SPI REG BUCK1 5.2.2 SPI REG BUCK2 5.2.3 SPI REG WD_REC_EN 5.2.4 SPI REG BUCK4 5.2.5 SPI REG BOOST VREF 5.2.6 SPI REG BUCK EN 5.2.7 SPI REG WD 5.2.8 SPI REG BUCK STAT1 5.2.9 SPI REG BUCK STAT2 5.2.10 SPI REG Fault Table PWUP 5.2.11 SPI REG ADC TH1 5.2.12 SPI REG ADC TH2 5.2.13 SPI REG ADC TH3 5.2.14 SPI REG ADC TH4 5.2.15 SPI REG ADC TH5 5.2.16 SPI REG ADC TH6 5.2.17 SPI REG ADC TH7 5.2.18 SPI REG ADC VBAT1 5.2.19 SPI REG ADC VBAT2 5.2.20 SPI REG OT Warning 5.2.21 SPI Fault STAT 5.2.22 SPI Silicon Version 5.2.23 SPI Device Identification 6 Device operating mode 6.1 Shutdown mode 6.2 Standby mode 6.3 INIT mode 6.4 REC mode 6.5 RAMPUP MAIN and SEC_UP 6.6 ACTIVE mode 6.7 OTP program mode 6.8 OTP bit mapping and register configuration 6.9 OTP (SAF) registers 6.9.1 SAF_REG_OP 6.9.2 SAF_REG_CFG 6.9.3 SAF_REG_DI 6.9.4 SAF_REG_D0_Bit_Ts 6.9.5 SAF_REG_STAT 6.10 Power down phase 6.11 Power up programming 7 Functional safety requirements 7.1 Functions and safety mechanism related to safety requirements 7.2 System safety mechanism 8 Application information 8.1 External components calculation 8.1.1 BUCK1 controller 8.1.1.1 RSENSE 8.1.1.2 BUCK1 output inductor 8.1.1.3 BUCK1 output capacitor 8.1.1.4 BUCK1 bootstrap capacitor 8.1.1.5 BUCK1 compensation network 8.1.2 BUCK2 controller 8.1.2.1 BUCK2 output inductor 8.1.2.2 BUCK2 output capacitor 8.1.2.3 BUCK2 compensation network 8.1.3 BUCK3, BUCK4 8.1.3.1 Output inductor and capacitor 8.1.3.2 Bootstrap capacitor for BUCK3 and BUCK4 8.1.3.3 Input capacitor 8.1.4 BOOST 8.1.4.1 BOOST output inductor 8.1.4.2 BOOST output capacitor 8.1.4.3 BOOST compensation network 8.1.4.4 Output diode for the BOOST converter 8.1.4.5 Input capacitor selection 8.2 PCB Layout example (BUCK1 as main regulator) 9 Package information 9.1 VFQFPN-48 (7x7x1.0 mm - opt. D) package information 9.2 VFQFPN-48 (7x7x1.0) marking information Revision history