Datasheet XP (IDT) - 7

XP Datasheet
Table 14. 3.3V AC Electrical Characteristics (Cont.)
VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol Parameter Test Condition Minimum Typical Maximum Units
LVDS. Differential. — 100 — Output Load LVPECL. V Ω DD - 2.0V. — 50 — HCSL. To GND. — 50 — Output valid time after V T DD meets minimum ST Start-up Time — 5 — ms specified level. LVDS. — 299 400 LVPECL. 20% – 80%, — 287 400 tR Output Rise Time ps 156.25MHz HCSL. — 306 400 CML — 301 400 LVDS. — 279 400 LVPECL. 80% – 20%, — 274 400 tF Output Fall Time ps 156.25MHz HCSL. — 284 400 CML — 279 400 LVDS. 156.25MHz 45 — 55 LVPECL. 156.25MHz 45 — 55 ODC Output Clock Duty Cycle % HCSL. 156.25MHz 45 — 55 CML 156.25MHz 45 — 55 TOE Output Enable/Disable Time — — — 1 — ms ©2019 Integrated Device Technology, Inc. 7 April 1, 2019 Document Outline Description Features Pin Assignments Figure 1. 7.0 × 5.0 mm, 5.0 × 3.2 mm, and 3.2 × 2.5 mm Packages Table 1. Pin Descriptions Absolute Maximum Ratings Table 2. Absolute Maximum Ratings ESD Compliance Table 3. ESD Compliance Mechanical Testing Table 4. Mechanical Testing * Solder Reflow Profile DC Electrical Characteristics Table 5. 3.3V IDD DC Electrical Characteristics Table 6. 2.5V IDD DC Electrical Characteristics Table 7. 1.8V IDD DC Electrical Characteristics Table 8. LVCMOS DC Electrical Characteristics Table 9. LVDS DC Electrical Characteristics Table 10. LVPECL DC Electrical Characteristics Table 11. HCSL DC Electrical Characteristics Table 12. CML DC Electrical Characteristics Table 13. DC Electrical Characteristics – Leakage Current AC Electrical Characteristics Table 14. 3.3V AC Electrical Characteristics Table 15. 2.5V AC Electrical Characteristics Table 16. 1.8V AC Electrical Characteristics Table 17. Phase Jitter Characteristics Output Waveforms Figure 2. LVDS Output Waveforms Figure 3. LVPECL Output Waveforms Figure 4. HCSL Output Waveforms Figure 5. CML Output Waveforms Termination for 3.3V LVPECL Outputs Figure 6. 3.3V LVPECL Output Termination Figure 7. 3.3V LVPECL Output Termination Termination for 2.5V LVPECL Outputs Figure 8. 2.5V LVPECL Driver Termination Example Figure 9. 2.5V LVPECL Driver Termination Example Figure 10. 2.5V LVPECL Driver Termination Example LVDS Driver Termination Figure 11. Standard LVDS Termination Figure 12. Optional LVDS Termination Recommended Termination for HCSL Outputs Figure 13. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 14. Recommended Termination (where a point-to-point connection can be used) CML Termination Figure 15. CML Termination Example Package Outline Drawings Marking Diagrams Figure 16. Marking Configuration for the 7.0 × 5.0 mm and 5.0 × 3.2 mm Packages Figure 17. Marking Configuration for the 3.2 × 2.5 mm Package Ordering Information Revision History