Datasheet ALT80600 (Allegro) - 2

制造商Allegro
描述LED Driver with Pre-Emptive Boost for Ultra-High Dimming Ratio and Low Output Ripple
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LED Driver with Pre-Emptive Boost. ALT80600 for Ultra-High Dimming Ratio and Low Output Ripple

LED Driver with Pre-Emptive Boost ALT80600 for Ultra-High Dimming Ratio and Low Output Ripple

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LED Driver with Pre-Emptive Boost ALT80600 for Ultra-High Dimming Ratio and Low Output Ripple FEATURES AND BENEFITS (continued) DESCRIPTION (continued)
• Excellent input voltage transient response even at lowest Switching frequency can be either above or below AM band. PWM duty cycle A programmable dithering feature further reduces EMI. A • Gate driver for optional PMOS input disconnect switch synchronization pin allows switching frequency to be synchronized • Extensive protection against: externally between 200 kHz and 2.3 MHz. A ‘Clock-Out’ pin allows □ Shorted boost switch, inductor or output capacitor other converters to be synchronized to the ALT80600’s switching □ Shorted FSET or ISET resistor frequency. □ Open or shorted LED pins and LED strings □ Open boost Schottky diode The ALT80600 provides protection against output short, overvoltage, □ Overtemperature open or shorted diode, open or shorted LED pin, and overtemperature. A cycle-by-cycle current limit protects the internal boost switch against high current overloads. An external P-MOSFET can optionally be used to disconnect input supply in case of output to ground short fault.
SELECTION GUIDE [1] Part Number Package Packing Leadframe Plating
ALT80600KESJSR 24-pin 4 × 4 mm wettable flank QFN with exposed thermal pad and sidewall plating 6000 pieces per reel 100% matte tin [1] Contact Allegro for additional packing options.
ABSOLUTE MAXIMUM RATINGS [2] Characteristi Symbol Notes Rating Unit
LEDx Pin VLEDx x = 1..4 –0.3 to 40 V OVP pin VOVP –0.3 to 40 V VIN VIN –0.3 to 40 V Higher of –0.3 VSENSE, GATE VSENSE, V and (VIN – 7.4) to V GATE VIN +0.4 Continuous –0.6 to 50 V SW VSW t < 50 ns (repetitious, <2.5 MHz) –1.0 to 54 V Single-event in case of Fault [3] –1.5 to 60 V FAULT VFAULT –0.3 to 40 V APWM, EN, PWM, CLKOUT, COMP, DITH, FSET, ISET, VDD, PEB –0.3 to 5.5 V Operating Ambient Temperature TA Range K –40 to 125 °C Maximum Junction Temperature TJ(max) 150 °C Storage Temperature Tstg –55 to 150 °C [2] Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. [3] SW DMOS is self-protecting and will conduct when VSW exceeds 60 V.
THERMAL CHARACTERISTICS:
May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions [4] Value Unit
Package Thermal Resistance RθJA ES package measured on 4-layer PCB based on JEDEC standard 37 °C/W [4] Additional thermal information available on the Allegro website. Allegro MicroSystems, LLC 2 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Applications Package Selection Guide Absolute Maximum Ratings Thermal Characteristics Typical Application – SEPIC Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Functional Description Enabling the IC Powering Up: LED Detection Phase Powering Up: Boost Output Undervoltage Soft Start Function Frequency Selection Synchronization Loss of External Sync Signal Switching Frequency Dithering Clock Out Function LED Current Setting PWM Dimming Pre-Emptive Boost (PEB) Analog Dimming with APWM Pin Extending LED Dimming Ratio Analog Dimming with External Voltage VDD Shutdown Fault Detection and Protection LED String Partial-Short Detect Boost Switch Overcurrent Protection Input Overcurrent Protection and Disconnect Switch Setting the Current Sense Resistor Input UVLO Fault Protection During Operation Fault Recovery Mechanism Package Outline Drawing Appendix A: Design Example