Datasheet ADuM4137 (Analog Devices) - 7

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Data Sheet ADuM4137 Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Fault Reporting Latch Assert Time A tLA_A 10 13 16 ms Latch Assert Time B tLA_B 18 20 23 ms Latch Assert Time C tLA_C 23 26 30 ms DRIVE SPECIFICATIONS Internal NFET On Resistance RDSON_N 0.51 0.95 Ω VOUT_OFF current (IVOUT_OFF) = 0.5 A, VDD1 = 6 V, VDD2 = 12 V On Resistance 2 Level RDSON_N_2LEV 1.78 3.45 Ω IVOUT_OFF = 0.1 A, VDD1 = 6 V, VDD2 = 12 V Internal PFET On Resistance RDSON_P 0.64 1.18 Ω VOUT_ON current (IVOUT_ON) = 0.5 A, VDD1 = 6 V, VDD2 = 12 V On Resistance 2 Level RDSON_P_2LEV 2.04 3.90 Ω IVOUT_ON = 0.1 A, VDD1 = 6 V, VDD2 = 12 V Miller Pull-Down NFET RDSON_MILLER 4 10 Ω Miller current (IMILLER) = 10 mA VOFF_SOFT RDSON RDSON_SOFT_OFF 15 33 Ω VOFF_SOFT current (IOFF_SOFT) = 10 mA Peak Current IPEAKIP 6 A VDD2 = 15 V, 2 Ω external resistance Two-Level Plateau Voltage V2LEV 11.67 11.89 12.05 V SWITCHING SPECIFICATIONS Pulse Width1 PW 70 ns VDD2 = 15 V, VOUT_ON = VOUT_OFF, no load Propagation Delay Rising2 tDLH 78 105 131 ns VDD2 = 15 V, VOUT_ON = VOUT_OFF, no load Falling2 tDHL 83 107 137 ns VDD2 = 15 V, VOUT_ON = VOUT_OFF, no load Dead Time tDEXT 0.91 1.00 1.11 µs 1 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 2 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 0% level of the VOUT_ON or VOUT_OFF signal. tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOUT_ON or VOUT_OFF signal. See Figure 13 for waveforms of propagation delay parameters. Rev. 0 | Page 7 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ELECTRICAL CHARACTERISTICS SPI TIMING SPECIFICATIONS SPI Timing Diagram PACKAGE CHARACTERISTICS REGULATORY INFORMATION INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION PCB LAYOUT SPI AND EEPROM OPERATION SPI Programming USER REGISTER MAP USER REGISTER BITS OFFSET_2[5:0] Bits GAIN_2[5:0] Bits OFFSET_1[5:0] Bits GAIN_1[5:0] Bits CONFIGURATION REGISTER BITS OT_FAULT_OP Bit OT_FAULT_SEL Bit OC_TIME_OP Bit OC_2LEV_OP Bit LOW_T_OP Bit OC_BLANK_OP Bit tBLANK[3:0] Bits ECC_OFF_OP Bit T_RAMP_OP Bit PWM_OSC CONTROL REGISTER BITS ECC2_DBL_ERR Bit ECC2_SNG_ERR Bit ECC1_DBL_ERR Bit ECC1_SNG_ERR Bit PROG_BUSY Bit SIM_TRIM Bit SPI SAFETY PROPAGATION DELAY RELATED PARAMETERS PROTECTION FEATURES Primary Side UVLO Fault Reporting Overcurrent Detection High Speed, Two-Level Turn Off Miller Clamp Thermal Shutdown ASC Pin Functionality Isolated Temperature Sensor Low Temperature Operation Mode FAULTB Pin DRIVER_FAULTB Pin UVLO_FAULTB Pin VDD2 UVLO Fault UVLO_FAULTB Fault, Gate Low Dead Time Control DRIVER_FAULTB Fault, Dead Time Fault Power Dissipation INSULATION LIFETIME DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS