Datasheet ADuM4138 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | High Voltage, Isolated IGBT Gate Driver with Isolated Flyback Controller |
| 页数 / 页 | 24 / 10 — ADuM4138. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 8. THERMAL … |
| 文件格式/大小 | PDF / 733 Kb |
| 文件语言 | 英语 |
ADuM4138. Data Sheet. ABSOLUTE MAXIMUM RATINGS Table 8. THERMAL RESISTANCE. Parameter. Rating. Table 9. Thermal Resistance
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ADuM4138 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 8. THERMAL RESISTANCE Parameter Rating
Thermal performance is directly linked to PCB design and Supply Voltages operating environment. Careful attention to PCB thermal VDD1 −0.2 V to +30 V design is required. VDD2 −0.2 V to +30 V θJA is the junction to ambient thermal resistance, and ΨJT is the Primary Side Pins junction to top characterization parameter. VI+, MOSI, CS, SCLK −0.2 V to +5.5 V SW, I
Table 9. Thermal Resistance
SENSE, FAULT, TEMP_OUT, −0.2 V to V5_1 + 0.2 V PGOOD, MISO
Package Type1 θJA
Ψ
JT Unit
Secondary Side Pins RN-28-1 62.4 2.97 °C/W TS1, TS2 −0.2 V to V5_2 + 0.2 V 1 4-layer PCB. MILLER_OUT, VOFF_SOFT, VOUT_OFF −0.2 V to + 30 V VOUT_ON, DESAT, GATE_SENSE, −0.2 V to VDD2 + 0.2 V OC1, OC2
ESD CAUTION
Common-Mode Transients (|CM|) −150 kV/µs to +150 kV/µs Storage Temperature Range (TST) −55°C to +150°C Operating Junction Temperature −40°C to +150°C Range Electrostatic Discharge (ESD) Human Body Model (HBM) ±1 kV Charge Device Model (CDM) ±1.25 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Table 10. Maximum Continuous Working Voltage1, 2, 3 Parameter Rating Constraint
AC Voltage Bipolar Waveform Basic Insulation 849 VPEAK Lifetime limited by insulation lifetime per VDE-0884-11 Reinforced Insulation 707 VPEAK Lifetime limited by insulation lifetime per VDE-0884-11 Unipolar Waveform Basic Insulation 1697 VPEAK Lifetime limited by insulation lifetime per VDE-0884-11 Reinforced Insulation 892 VPEAK Lifetime limited by package creepage per IEC 60664-1 DC Voltage Basic Insulation 1092 VPEAK Lifetime limited by package creepage per IEC 60664-1 Reinforced Insulation 546 VPEAK Lifetime limited by package creepage per IEC 60664-1 1 See the Insulation Lifetime section for details. 2 Other pollution degree and material group requirements yield a different limit. 3 Some system level standards allow components to use the printed wiring board (PWB) creepage values. The supported dc voltage may be higher for those standards.
Table 11. Truth Table (Positive Logic) VI+ Input FAULT Pin VDD1 State VDD2 State GATE_SENSE Voltage (VGATE_SENSE)
Low High Powered Powered Low High High Powered Powered High Don’t Care or Unknown Low Powered Powered Low Don’t Care or Unknown Don’t care or unknown Unpowered Powered Low Don’t Care or Unknown Low Powered Unpowered High-Z Rev. 0 | Page 10 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ELECTRICAL CHARACTERISTICS SPI TIMING SPECIFICATIONS SPI Timing Diagram PACKAGE CHARACTERISTICS REGULATORY INFORMATION (PENDING) INSULATION AND SAFETY-RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10):2016-12 INSULATION CHARACTERISTICS (PENDING) RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION PCB LAYOUT ISOLATED FLYBACK CONTROLLER SPI AND EEPROM OPERATION SPI Programming USER REGISTER MAP USER REGISTER BITS OFFSET_2[5:0] Bits GAIN_2[5:0] Bits OFFSET_1[5:0] Bits GAIN_1[5:0] Bits CONFIGURATION REGISTER BITS OT_FAULT_OP Bit OT_FAULT_SEL Bit OC_TIME_OP Bit OC_2LEV_OP Bits LOW_T_OP Bit OC_BLANK_OP Bit tBLANK[3:0] Bits ECC_OFF_OP Bit FLYBACK_V[3:0] Bits T_RAMP_OP Bit PWM_OSC Bit CONTROL REGISTER BITS ECC2_DBL_ERR Bit ECC2_SNG_ERR Bit ECC1_DBL_ERR Bit ECC1_SNG_ERR Bit PROG_BUSY Bit SIM_TRIM Bit PROPAGATION DELAY RELATED PARAMETERS PROTECTION FEATURES Primary Side UVLO Fault Reporting Overcurrent Detection High Speed, Two-Level, Turn Off Miller Clamp Desaturation Detection Thermal Shutdown Isolated Temperature Sensor POWER DISSIPATION INSULATION LIFETIME DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
ADuM4138 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 8. THERMAL RESISTANCE Parameter Rating
Thermal performance is directly linked to PCB design and Supply Voltages operating environment. Careful attention to PCB thermal VDD1 −0.2 V to +30 V design is required. VDD2 −0.2 V to +30 V θJA is the junction to ambient thermal resistance, and ΨJT is the Primary Side Pins junction to top characterization parameter. VI+, MOSI, CS, SCLK −0.2 V to +5.5 V SW, I
Table 9. Thermal Resistance
SENSE, FAULT, TEMP_OUT, −0.2 V to V5_1 + 0.2 V PGOOD, MISO
Package Type1 θJA
Ψ
JT Unit
Secondary Side Pins RN-28-1 62.4 2.97 °C/W TS1, TS2 −0.2 V to V5_2 + 0.2 V 1 4-layer PCB. MILLER_OUT, VOFF_SOFT, VOUT_OFF −0.2 V to + 30 V VOUT_ON, DESAT, GATE_SENSE, −0.2 V to VDD2 + 0.2 V OC1, OC2
ESD CAUTION
Common-Mode Transients (|CM|) −150 kV/µs to +150 kV/µs Storage Temperature Range (TST) −55°C to +150°C Operating Junction Temperature −40°C to +150°C Range Electrostatic Discharge (ESD) Human Body Model (HBM) ±1 kV Charge Device Model (CDM) ±1.25 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Table 10. Maximum Continuous Working Voltage1, 2, 3 Parameter Rating Constraint
AC Voltage Bipolar Waveform Basic Insulation 849 VPEAK Lifetime limited by insulation lifetime per VDE-0884-11 Reinforced Insulation 707 VPEAK Lifetime limited by insulation lifetime per VDE-0884-11 Unipolar Waveform Basic Insulation 1697 VPEAK Lifetime limited by insulation lifetime per VDE-0884-11 Reinforced Insulation 892 VPEAK Lifetime limited by package creepage per IEC 60664-1 DC Voltage Basic Insulation 1092 VPEAK Lifetime limited by package creepage per IEC 60664-1 Reinforced Insulation 546 VPEAK Lifetime limited by package creepage per IEC 60664-1 1 See the Insulation Lifetime section for details. 2 Other pollution degree and material group requirements yield a different limit. 3 Some system level standards allow components to use the printed wiring board (PWB) creepage values. The supported dc voltage may be higher for those standards.
Table 11. Truth Table (Positive Logic) VI+ Input FAULT Pin VDD1 State VDD2 State GATE_SENSE Voltage (VGATE_SENSE)
Low High Powered Powered Low High High Powered Powered High Don’t Care or Unknown Low Powered Powered Low Don’t Care or Unknown Don’t care or unknown Unpowered Powered Low Don’t Care or Unknown Low Powered Unpowered High-Z Rev. 0 | Page 10 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ELECTRICAL CHARACTERISTICS SPI TIMING SPECIFICATIONS SPI Timing Diagram PACKAGE CHARACTERISTICS REGULATORY INFORMATION (PENDING) INSULATION AND SAFETY-RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10):2016-12 INSULATION CHARACTERISTICS (PENDING) RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION PCB LAYOUT ISOLATED FLYBACK CONTROLLER SPI AND EEPROM OPERATION SPI Programming USER REGISTER MAP USER REGISTER BITS OFFSET_2[5:0] Bits GAIN_2[5:0] Bits OFFSET_1[5:0] Bits GAIN_1[5:0] Bits CONFIGURATION REGISTER BITS OT_FAULT_OP Bit OT_FAULT_SEL Bit OC_TIME_OP Bit OC_2LEV_OP Bits LOW_T_OP Bit OC_BLANK_OP Bit tBLANK[3:0] Bits ECC_OFF_OP Bit FLYBACK_V[3:0] Bits T_RAMP_OP Bit PWM_OSC Bit CONTROL REGISTER BITS ECC2_DBL_ERR Bit ECC2_SNG_ERR Bit ECC1_DBL_ERR Bit ECC1_SNG_ERR Bit PROG_BUSY Bit SIM_TRIM Bit PROPAGATION DELAY RELATED PARAMETERS PROTECTION FEATURES Primary Side UVLO Fault Reporting Overcurrent Detection High Speed, Two-Level, Turn Off Miller Clamp Desaturation Detection Thermal Shutdown Isolated Temperature Sensor POWER DISSIPATION INSULATION LIFETIME DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS