Datasheet PI4GTL2002 (Diodes) - 4
| 制造商 | Diodes |
| 描述 | 2-CHANNEL Gtl Level Shifter & Transceiver |
| 页数 / 页 | 13 / 4 — PI4GTL2002. DC Electrical Characteristics. Parameter. Description. Test … |
| 文件格式/大小 | PDF / 1.4 Mb |
| 文件语言 | 英语 |
PI4GTL2002. DC Electrical Characteristics. Parameter. Description. Test Conditions(1). Min. Typ.(2). Max. Unit
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文件文字版本
PI4GTL2002 DC Electrical Characteristics
TA = -40 C to +85 C; unless otherwise specified
Parameter Description Test Conditions(1) Min Typ.(2) Max Unit Input and output DB and SB
VIK input clamping voltage II = -18mA; VGREF = 0 V - - -1.2 V IIH HIGH-level input current VI = 5 V; VGREF = 0 V - - 5 µA CGREF input capacitance on pin GREF VI = 3 V or 0 V - 11 - pF off-state input/output capacitance Cio(off) V (Sn, Dn) O = 3 V or 0 V; VGREF = 0 V - 4 - pF on-state input/output capacitance Cio(on) V (Sn, Dn) O = 3 V or 0 V; VGREF = 3 V - 10.5 - pF VGREF = 4.5 V - 3.5 5.5 Ω V VGREF = 3 V - 4.7 7.0 Ω I = 0V; IO = 64mA VGREF = 2.3 V - 6.3 9.5 Ω ON-state resistance(2) Ron VGREF = 1.5 V - 60 140 Ω (Sn, Dn) V VGREF = 4.5 V 1 6 15 Ω I = 2.4V; IO = 15mA VGREF = 3 V 20 60 140 Ω VI = 1.7V; V I GREF = 2.3 V 20 60 140 Ω O = 15mA
Notes:
1) All typical values are at TA = 25 °C. 2) Measured by the voltage drop between the S1 and S2, or D1 and D2 terminals at the indicated current through the switch. ON-state resistance is determined by the lowest voltage of the two terminals.
Dynamic Characteristics
TA = -40 C to +85 C; unless otherwise specified. Values guaranteed by design.
CL = 50 pF CL = 30 pF CL = 15 pF Symbol Parameter Conditions Unit Min Max Min Max Min Max
VGREF = 3.3 V; VH = 3.3 V; VL = 0 V; VM = 1.15 V LOW-to-HIGH from (input) S2 or D2 tPLH 0 0.8 0 0.6 0 0.3 ns propagation delay to (output) S1 or D1 HIGH-to-LOW from (input) S2 or D2 tPHL 0 1.2 0 1 0 0.5 ns propagation delay to (output) S1 or D1 VGREF = 2.5 V; VH = 2.5 V; VL = 0 V; VM = 0.75 V LOW-to-HIGH from (input) S2 or D2 tPLH 0 1 0 0.7 0 0.4 ns propagation delay to (output) S1 or D1 HIGH-to-LOW from (input) S2 or D2 tPHL 0 1.3 0 1 0 0.6 ns propagation delay to (output) S1 or D1 VGREF = 3.3 V; VH = 2.3 V; VL = 0 V; VT = 3.3 V; VM = 1.15 V; RL = 300 Ω LOW-to-HIGH ffrom (input) S1 orD1 tPLH 0 0.9 0 0.6 0 0.4 ns propagation delay to (output) S2 or D2 HIGH-to-LOW from (input) S1 or D1 tPHL 0 1.4 0 1.1 0 0.7 ns propagation delay to (output) S2 or D2 VGREF = 2.5 V; VH = 1.5 V; VL = 0 V; VT = 2.5 V; VM = 0.75 V; RL = 300 Ω LOW-to-HIGH from (input) S1 orD1 tPLH 0 1 0 0.6 0 0.4 ns propagation delay to (output) S2 or D2 HIGH-to-LOW from (input) S1 or D1 tPHL 0 1.3 0 1.3 0 0.8 ns propagation delay to (output) S2 or D2 PI4GTL2002
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October 2018 Document Number DS40704 Rev 2-2 4 © Diodes Incorporated
TA = -40 C to +85 C; unless otherwise specified
Parameter Description Test Conditions(1) Min Typ.(2) Max Unit Input and output DB and SB
VIK input clamping voltage II = -18mA; VGREF = 0 V - - -1.2 V IIH HIGH-level input current VI = 5 V; VGREF = 0 V - - 5 µA CGREF input capacitance on pin GREF VI = 3 V or 0 V - 11 - pF off-state input/output capacitance Cio(off) V (Sn, Dn) O = 3 V or 0 V; VGREF = 0 V - 4 - pF on-state input/output capacitance Cio(on) V (Sn, Dn) O = 3 V or 0 V; VGREF = 3 V - 10.5 - pF VGREF = 4.5 V - 3.5 5.5 Ω V VGREF = 3 V - 4.7 7.0 Ω I = 0V; IO = 64mA VGREF = 2.3 V - 6.3 9.5 Ω ON-state resistance(2) Ron VGREF = 1.5 V - 60 140 Ω (Sn, Dn) V VGREF = 4.5 V 1 6 15 Ω I = 2.4V; IO = 15mA VGREF = 3 V 20 60 140 Ω VI = 1.7V; V I GREF = 2.3 V 20 60 140 Ω O = 15mA
Notes:
1) All typical values are at TA = 25 °C. 2) Measured by the voltage drop between the S1 and S2, or D1 and D2 terminals at the indicated current through the switch. ON-state resistance is determined by the lowest voltage of the two terminals.
Dynamic Characteristics
TA = -40 C to +85 C; unless otherwise specified. Values guaranteed by design.
CL = 50 pF CL = 30 pF CL = 15 pF Symbol Parameter Conditions Unit Min Max Min Max Min Max
VGREF = 3.3 V; VH = 3.3 V; VL = 0 V; VM = 1.15 V LOW-to-HIGH from (input) S2 or D2 tPLH 0 0.8 0 0.6 0 0.3 ns propagation delay to (output) S1 or D1 HIGH-to-LOW from (input) S2 or D2 tPHL 0 1.2 0 1 0 0.5 ns propagation delay to (output) S1 or D1 VGREF = 2.5 V; VH = 2.5 V; VL = 0 V; VM = 0.75 V LOW-to-HIGH from (input) S2 or D2 tPLH 0 1 0 0.7 0 0.4 ns propagation delay to (output) S1 or D1 HIGH-to-LOW from (input) S2 or D2 tPHL 0 1.3 0 1 0 0.6 ns propagation delay to (output) S1 or D1 VGREF = 3.3 V; VH = 2.3 V; VL = 0 V; VT = 3.3 V; VM = 1.15 V; RL = 300 Ω LOW-to-HIGH ffrom (input) S1 orD1 tPLH 0 0.9 0 0.6 0 0.4 ns propagation delay to (output) S2 or D2 HIGH-to-LOW from (input) S1 or D1 tPHL 0 1.4 0 1.1 0 0.7 ns propagation delay to (output) S2 or D2 VGREF = 2.5 V; VH = 1.5 V; VL = 0 V; VT = 2.5 V; VM = 0.75 V; RL = 300 Ω LOW-to-HIGH from (input) S1 orD1 tPLH 0 1 0 0.6 0 0.4 ns propagation delay to (output) S2 or D2 HIGH-to-LOW from (input) S1 or D1 tPHL 0 1.3 0 1.3 0 0.8 ns propagation delay to (output) S2 or D2 PI4GTL2002
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October 2018 Document Number DS40704 Rev 2-2 4 © Diodes Incorporated