Datasheet A3955 (Allegro) - 8

A3955 Full-Bridge PWM Microstepping Motor Driver Functional Description
which turns off the source drivers (slow-decay mode) or the sink and source drivers (fast- or mixed-decay mode). Two A3955 full-bridge PWM microstepping motor drivers are needed to drive the windings of a bipolar stepper motor. Internal With the DATA input lines tied to VCC, the maximum value of pulse width modulated (PWM) control circuitry regulates each current limiting is set by the selection of RS and VREF with a motor winding current. The peak motor current is set by the transconductance function approximated by: value of an external current-sense resistor (RS), a reference I voltage (V TRIP ≈ VREF / 3RS. REF), and the digital-to-analog converter (DAC) data inputs (D The actual peak load current (I 0, D1, and D2). PEAK) will be slightly higher than I To improve motor performance, especially when using TRIP due to internal logic and switching delays. The driver(s) remain off for a time period determined by a user-selected sinusoidal current profi les necessary for microstepping, the external resistor-capacitor combination (R A3955 has three distinct current-decay modes: slow decay, fast TCT). At the end of the fi xed off-time, the driver(s) are re-enabled, allowing the load decay, and mixed decay. current to increase to ITRIP again, maintaining an average load
PHASE Input.
The PHASE input controls the direction of current. current fl ow in the load (table 1). An internally generated dead The DAC data input lines are used to provide up to eight levels time of approximately 1 μs prevents crossover currents that of output current. The internal 3-bit digital-to-analog converter could occur when switching the PHASE input. reduces the reference input to the current-sense comparator
DAC Data Inputs (D
in precise steps (the step reference current ratio or SRCR) to
0, D1, D2).
A non-linear DAC is used to digitally control the output current. The output of the DAC is provide half-step, quarter-step, or “microstepping” load-current used to set the trip point of the current-sense comparator. Table 3 levels. shows DAC output voltages for each input condition. When D0, I D TRIP ≈ SRCR x VREF/3RS 1, and D2 are all logic low, all of the power output transistors are turned off.
Slow Current-Decay Mode.
When VPFD ≥ 3.5 V, the device is in slow current-decay mode (the source drivers are
Internal PWM Current Control.
Each motor driver disabled when the load current reaches I contains an internal fi xed off-time PWM current-control circuit TRIP). During the fi xed off-time, the load inductance causes the current to recirculate that limits the load current to a desired value (ITRIP). Initially, through the motor winding, sink driver, ground clamp diode, a diagonal pair of source and sink transistors are enabled and and sense resistor (see fi gure 1). Slow-decay mode produces current fl ows through the motor winding and RS (fi gure 1). When low ripple current for a given fi xed off-time (see fi gure 2). the voltage across the sense resistor equals the DAC output Low ripple current is desirable because the average current voltage the current-sense comparator resets the PWM latch, in the motor winding is more nearly equal to the desired VBB I PEAK SLOW (V ≥ 3.5 V) PFD MIXED (1.1 V ≤ V ≤ 3.1 V) DRIVE CURRENT PFD RECIRCULATION FAST (V ≤ 0.8 V) (SLOW-DECAY MODE) PFD PFD RECIRCULATION (FAST-DECAY MODE) t OFF Dwg. WP-031-1 RS Dwg. EP-006-15
Figure 1 — Load-Current Paths Figure 2 — Current-Decay Waveforms
Allegro MicroSystems, Inc. 7 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com