Datasheet ADN2805 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 1.25 Gbps Clock and Data Recovery IC |
| 页数 / 页 | 16 / 3 — Data Sheet. ADN2805. SPECIFICATIONS. Table 1. Parameter Conditions. Min. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 293 Kb |
| 文件语言 | 英语 |
Data Sheet. ADN2805. SPECIFICATIONS. Table 1. Parameter Conditions. Min. Typ. Max. Unit. JITTER SPECIFICATIONS
该数据表的模型线
文件文字版本
Data Sheet ADN2805 SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted.
Table 1. Parameter Conditions Min Typ Max Unit
QUANTIZER—DC CHARACTERISTICS Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V Peak-to-Peak Differential Input PIN − NIN 0.2 2.0 V Input Common-Mode Level DC-coupled 2.3 2.5 2.8 V QUANTIZER—AC CHARACTERISTICS Data Rate 1250 Mbps S11 @ 2.5 GHz −15 dB Input Resistance Differential 100 Ω Input Capacitance 0.65 pF LOSS-OF-LOCK (LOL) DETECT VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm LOL Response Time 200 μs ACQUISITION TIME Lock-to-Data Mode GbE 1.5 ms Optional Lock to REFCLK Mode 20.0 ms DATA RATE READBACK ACCURACY Fine Readback In addition to REFCLK accuracy 100 ppm POWER SUPPLY Power Supply Voltage 3.0 3.3 3.6 V Power Supply Current Locked to 1.25 Gbps 118 131 mA OPERATING TEMPERATURE RANGE −40 +85 °C
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted.
Table 2. Parameter Conditions Min Typ Max Unit
PHASE-LOCKED LOOP CHARACTERISTICS Jitter Peaking 0 0.03 dB Jitter Generation 0.001 0.003 UI rms 0.02 0.04 UI p-p Jitter Tolerance GbE, IEEE 802.3, 637 kHz 0.749 UI p-p Rev. B | Page 3 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS JITTER SPECIFICATIONS OUTPUT AND TIMING SPECIFICATIONS Timing Characteristics ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Thermal Resistance ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION THEORY OF OPERATION FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION INPUT BUFFER LOCK DETECTOR OPERATION Normal Mode LOL Detector Operation Using a Reference Clock Static LOL Mode SQUELCH MODE SYSTEM RESET I2C INTERFACE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes Transmission Lines Soldering Guidelines for Lead Frame Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted.
Table 1. Parameter Conditions Min Typ Max Unit
QUANTIZER—DC CHARACTERISTICS Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V Peak-to-Peak Differential Input PIN − NIN 0.2 2.0 V Input Common-Mode Level DC-coupled 2.3 2.5 2.8 V QUANTIZER—AC CHARACTERISTICS Data Rate 1250 Mbps S11 @ 2.5 GHz −15 dB Input Resistance Differential 100 Ω Input Capacitance 0.65 pF LOSS-OF-LOCK (LOL) DETECT VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm VCO Frequency Error for LOL Deassert With respect to nominal 250 ppm LOL Response Time 200 μs ACQUISITION TIME Lock-to-Data Mode GbE 1.5 ms Optional Lock to REFCLK Mode 20.0 ms DATA RATE READBACK ACCURACY Fine Readback In addition to REFCLK accuracy 100 ppm POWER SUPPLY Power Supply Voltage 3.0 3.3 3.6 V Power Supply Current Locked to 1.25 Gbps 118 131 mA OPERATING TEMPERATURE RANGE −40 +85 °C
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted.
Table 2. Parameter Conditions Min Typ Max Unit
PHASE-LOCKED LOOP CHARACTERISTICS Jitter Peaking 0 0.03 dB Jitter Generation 0.001 0.003 UI rms 0.02 0.04 UI p-p Jitter Tolerance GbE, IEEE 802.3, 637 kHz 0.749 UI p-p Rev. B | Page 3 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS JITTER SPECIFICATIONS OUTPUT AND TIMING SPECIFICATIONS Timing Characteristics ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Thermal Resistance ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION THEORY OF OPERATION FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION INPUT BUFFER LOCK DETECTOR OPERATION Normal Mode LOL Detector Operation Using a Reference Clock Static LOL Mode SQUELCH MODE SYSTEM RESET I2C INTERFACE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes Transmission Lines Soldering Guidelines for Lead Frame Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE