Datasheet LTC2344-16 (Analog Devices) - 8

link to page 13 LTC2344-16
ADC TIMING CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 10:
Guaranteed by design, not subject to test. may cause permanent damage to the device. Exposure to any Absolute
Note 11:
For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is Maximum Rating condition for extended periods may affect device the offset voltage measured from –0.5LSB when the output code flickers reliability and lifetime. between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale
Note 2:
All voltage values are with respect to ground. error for these SoftSpan ranges is the worst-case deviation of the first and
Note 3:
V last code transitions from ideal and includes the effect of offset error. For DDLBYP is the output of an internal voltage regulator, and should only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND, unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is the offset voltage as described in the Pin Functions section. Do not connect this pin to any measured from 0.5LSB when the output code flickers between 0000 0000 external circuitry. 0000 0000 and 0000 0000 0000 0001. Full-scale error for these SoftSpan
Note 4:
When these pin voltages are taken below ground or above V ranges is the worst-case deviation of the last code transition from ideal DD or OV and includes the effect of offset error. DD, they will be clamped by internal diodes. This product can handle currents of up to 100mA below ground or above V
Note 12:
All specifications in dB are referred to a full-scale input in the DD or OVDD without latch-up. relevant SoftSpan input range, except for crosstalk, which is referred to
Note 5:
V the crosstalk injection signal amplitude. DD = 5V unless otherwise specified.
Note 6:
Recommended operating conditions.
Note 13:
Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range.
Note 7:
Exceeding these limits on any channel may corrupt conversion results on other channels. Refer to Absolute Maximum Ratings section for
Note 14:
When REFBUF is overdriven, the internal reference buffer must pin voltage limits related to device reliability. be disabled by setting REFIN = 0V.
Note 8:
V
Note 15:
I DD = 5V, OVDD = 2.5V, fSMPL = 400ksps, internal reference and REFBUF varies proportionally with sample rate and the number of buffer, fully differential input signal drive in SoftSpan ranges 7 and 6, active channels. bipolar input signal drive in SoftSpan ranges 3 and 2, unipolar input signal
Note 16:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V, drive in SoftSpan ranges 5, 4 and 1, unless otherwise specified. and OVDD = 5.25V.
Note 9:
Integral nonlinearity is defined as the deviation of a code from a
Note 17:
A tSCKI period of 10ns minimum allows a shift clock frequency of straight line passing through the actual endpoints of the transfer curve. up to 100MHz for rising edge capture. The deviation is measured from the center of the quantization band.
Note 18:
VICM = 1.2V, VID = 350mV for LVDS differential input pairs.
CMOS Timings
0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 234416 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
LVDS Timings (Differential)
+200mV tWIDTH –200mV t tDELAY 0V 0V DELAY 234416 F01b +200mV +200mV –200mV –200mV
Figure 1. Voltage Levels for Timing Specifications
Rev A 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Configuration Tables Functional Block Diagrams Timing Diagram Applications Information Package Description Revision History Typical Application Related Parts