Datasheet ADAR7251 (Analog Devices) - 4

ADAR7251 Data Sheet FUNCTIONAL BLOCK DIAGRAM DD3 AL ,AV IT G DD2 DD2 DD2 V _DI ,AV D UT ,DV 1,IO O D VD DD1 G DD1 D L PL AV RE DV IOV AVDD PLLVDD AVDD BIASP BIAS GENERATOR DVDD BIASN AVDD VOLTAGE ADC_DOUT0 CM REFERENCE REGULATOR ADC_DOUT1 ADC_DOUT2/GPIO1 AIN1P LNA PGA EQ CH1 DIGITAL Σ-∆ ADC AIN1N FILTER ADC_DOUT3/GPIO2 ADC ADC_DOUT4 S R ADC_DOUT5 AIN2P DIGITAL O DIGITAL LNA PGA EQ ADDR15/ADC_DOUT6 AIN2N CH2 Σ-∆ ADC FILTER AT INTERFACE M FS_ADC/ADC_DOUT7 CI SCLK_ADC DE AIN3P DIGITAL CONV_START LNA PGA EQ AIN3N CH3 Σ-∆ ADC FILTER DATA_READY FAULT AIN4P LNA PGA EQ CH4 DIGITAL AIN4N Σ-∆ ADC FILTER SPI_MISO SPI SPI_MOSI CONTROL SPI_CLK SPI_SS AUXIN1 X AUX ADC AUXIN2 AVDD DVDD MU PLLVDD RESET POR RESET, PWDN OSCILLATOR PLL ADAR7251 T IN D 3 U K LT N L ND ND2 XO LFI LLG L /MC P P DG , AG N XI ND2, ND1 AG , DG
1 00 7-
ND1
35
G
12
D
Figure 1. Rev. 0 | Page 4 of 72 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Analog Channel Digital Input/Output Power Supply Digital Filter SPI Port Timing Serial/Peripheral Parallel Interface (PPI) Port Timing Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Low Speed Ramp Radar Analog Front End Main Channel Overview Σ-∆ Modulation and Digital Filtering Differential Input Configuration High-Pass Filter (HPF) Low-Pass Filter (LPF) Input Routing Equalizer (EQ) Using LNA/PGA, EQ, or the Input Capacitor Reference Auxiliary ADC Power Supply LDO Clock Requirements Crystal Oscillator PLL Integer Mode Fractional Mode PLL Lock Acquisition GPIO ADC Data Port ADC Serial Mode ADC Serial Master Mode ADC Serial Master Mode with ADC Serial Slave ADC PPI (Byte Wide Mode) ADC PPI Nibble Wide Mode DAQ Mode Using Multiple ADAR7251 Devices for Systems with More Than Four Channels Device Address R/ Register Address Data Bytes CRC PCB Layout Guidelines Register Summary Register Details Clock Control Register PLL Denominator Register PLL Numerator Register PLL Control Register PLL Status Register Master Enable Switch Register ADC Enable Register Power Enable Register Clear the ASIL errors Register Selects Which Errors to Mask Register ASIL Error Flag Register ASIL Error Code Register CRC Value, Bits[7:0] Register CRC Value Register Start Calculating the CRC Value of the Register Map Content Register Register Map CRC Calculation Done Register Register Map CRC Value, Bits[7:0] Register Register Map CRC Value, Bits[15:8] Register Low Noise Amplifier Gain Control Register Programmable Gain Amplifier Gain Control Register Signal Path for ADC 1 Through ADC 4 Register Decimator Rate Control Register High Pass Filter Control Register DAQ Mode Control Register Decimator Truncate Control Register Serial Output Port Control Register Parallel Port Control Register ADC Digital Output Mode Register Auxiliary ADC Read Value Registers Auxiliary ADC Sample Rate Selection Register Auxiliary ADC Mode Register MPx Pin Modes Registers MP Write Value Registers MP Read Value Registers SPI_CLK Pin Drive Strength and Slew Rate Register SPI_MISO Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SPI_MOSI Pin Drive Strength and Slew Rate Register ADDR15 Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register FS_ADC Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SCLK_ADC Pin Drive Strength and Slew Rate Register ADC_DOUTx Pins Drive Strength and Slew Rate Registers DATA_READY Pin Drive Strength and Slew Rate Register XTAL Enable and Drive Register ADC Test Register Digital Filter Sync Enable Register CRC Enable/Disable Register Typical Application Circuit Outline Dimensions Ordering Guide Automotive Products