Datasheet ADAS3022-EP (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 1 MSPS, 8 Channel Data Acquisition System |
| 页数 / 页 | 21 / 4 — ADAS3022-EP. Enhanced Product. SPECIFICATIONS. Table 2. Parameter. Test … |
| 文件格式/大小 | PDF / 487 Kb |
| 文件语言 | 英语 |
ADAS3022-EP. Enhanced Product. SPECIFICATIONS. Table 2. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit1
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ADAS3022-EP Enhanced Product SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%, VIO = 1.8 V to AVDD, internal voltage reference (VREF) = 4.096 V, sampling frequency (fS) = 1 MSPS unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Test Conditions/Comments Min Typ Max Unit1
RESOLUTION 16 Bits ANALOG INPUTS—IN[7:0], COM Operating Input Voltage Range VIN −VSSH + 2.5 VDDH − 2.5 V Differential Input Voltage Range, VIN VIN+ − VIN− PGIA gain = 0.16, VIN = 49.15 V p-p −6 × VREF +6 × VREF V PGIA gain = 0.2, VIN = 40.96 V p-p −5 × VREF +5 × VREF V PGIA gain = 0.4, VIN = 20.48 V p-p −2.5 × VREF +2.5 × VREF V PGIA gain = 0.8, VIN = 10.24 V p-p −1.25 × VREF +1.25 × VREF V PGIA gain = 1.6, VIN = 5.12 V p-p −0.625 × VREF +0.625 × VREF V PGIA gain = 3.2, VIN = 2.56 V p-p −0.3125 × VREF +0.3125 × VREF V PGIA gain = 6.4, VIN = 1.28 V p-p −0.1563 × VREF +0.1563 × VREF V Input Impedance, ZIN 500 MΩ Channel Off Leakage ±0.6 nA Channel On Leakage ±0.02 nA Common-Mode Voltage Range VIN+, VIN−; full-scale differential inputs (VCM)2 PGIA gain = 0.4 −5.12 +5.12 V PGIA gain = 0.8 −7.68 +7.68 V PGIA gain = 1.6 −8.96 +8.96 V PGIA gain = 3.2 −9.60 +9.60 V PGIA gain = 6.4 −9.92 +9.92 V ANALOG INPUTS—AUX+, AUX− Differential Input Voltage Range −VREF +VREF V THROUGHPUT Conversion Rate One channel and one pair 0 1000 kSPS Two channels and two pairs 0 500 kSPS Four channels and four pairs 0 250 kSPS Eight channels 0 125 kSPS Transient Response Full-scale step 520 ns DC ACCURACY No Missing Codes 16 Bits Integral Linearity Error PGIA gain = 0.16, 0.2, 0.4, 0.8, and 1.6 −2 ±0.6 +2 LSB PGIA gain = 3.2 −3 ±1.0 +3 LSB PGIA gain = 6.4 −5 ±1.5 +5 LSB Differential Linearity Error PGIA gain = 0.16, 0.2, 0.4, 0.8, and 1.6 −0.9 ±0.6 +1.0 LSB PGIA gain = 3.2 −0.9 ±0.75 +1.25 LSB PGIA gain = 6.4 −0.9 ±0.75 +1.25 LSB Transition Noise External reference PGIA gain = 0.16, 0.2, 0.4, 0.8, and 1.6 5 LSB PGIA gain = 3.2 7 LSB PGIA gain = 6.4 11 LSB Gain Error External reference, all PGIA gains, TA = 25°C −9 +9 LSB Gain Error Temperature Drift External reference, all PGIA gains 0.1 ppm/°C Rev. 0 | Page 4 of 21 Document Outline Features Enhanced Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide
ADAS3022-EP Enhanced Product SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%, VIO = 1.8 V to AVDD, internal voltage reference (VREF) = 4.096 V, sampling frequency (fS) = 1 MSPS unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Test Conditions/Comments Min Typ Max Unit1
RESOLUTION 16 Bits ANALOG INPUTS—IN[7:0], COM Operating Input Voltage Range VIN −VSSH + 2.5 VDDH − 2.5 V Differential Input Voltage Range, VIN VIN+ − VIN− PGIA gain = 0.16, VIN = 49.15 V p-p −6 × VREF +6 × VREF V PGIA gain = 0.2, VIN = 40.96 V p-p −5 × VREF +5 × VREF V PGIA gain = 0.4, VIN = 20.48 V p-p −2.5 × VREF +2.5 × VREF V PGIA gain = 0.8, VIN = 10.24 V p-p −1.25 × VREF +1.25 × VREF V PGIA gain = 1.6, VIN = 5.12 V p-p −0.625 × VREF +0.625 × VREF V PGIA gain = 3.2, VIN = 2.56 V p-p −0.3125 × VREF +0.3125 × VREF V PGIA gain = 6.4, VIN = 1.28 V p-p −0.1563 × VREF +0.1563 × VREF V Input Impedance, ZIN 500 MΩ Channel Off Leakage ±0.6 nA Channel On Leakage ±0.02 nA Common-Mode Voltage Range VIN+, VIN−; full-scale differential inputs (VCM)2 PGIA gain = 0.4 −5.12 +5.12 V PGIA gain = 0.8 −7.68 +7.68 V PGIA gain = 1.6 −8.96 +8.96 V PGIA gain = 3.2 −9.60 +9.60 V PGIA gain = 6.4 −9.92 +9.92 V ANALOG INPUTS—AUX+, AUX− Differential Input Voltage Range −VREF +VREF V THROUGHPUT Conversion Rate One channel and one pair 0 1000 kSPS Two channels and two pairs 0 500 kSPS Four channels and four pairs 0 250 kSPS Eight channels 0 125 kSPS Transient Response Full-scale step 520 ns DC ACCURACY No Missing Codes 16 Bits Integral Linearity Error PGIA gain = 0.16, 0.2, 0.4, 0.8, and 1.6 −2 ±0.6 +2 LSB PGIA gain = 3.2 −3 ±1.0 +3 LSB PGIA gain = 6.4 −5 ±1.5 +5 LSB Differential Linearity Error PGIA gain = 0.16, 0.2, 0.4, 0.8, and 1.6 −0.9 ±0.6 +1.0 LSB PGIA gain = 3.2 −0.9 ±0.75 +1.25 LSB PGIA gain = 6.4 −0.9 ±0.75 +1.25 LSB Transition Noise External reference PGIA gain = 0.16, 0.2, 0.4, 0.8, and 1.6 5 LSB PGIA gain = 3.2 7 LSB PGIA gain = 6.4 11 LSB Gain Error External reference, all PGIA gains, TA = 25°C −9 +9 LSB Gain Error Temperature Drift External reference, all PGIA gains 0.1 ppm/°C Rev. 0 | Page 4 of 21 Document Outline Features Enhanced Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide