Datasheet AD7689-KGD (Analog Devices) - 7

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Known Good Die AD7689-KGD
VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 4. Parameter1 Symbol Min Typ Max Unit
CONVERSION TIME tCONV CNV Rising Edge to Data Available 3.4 µs ACQUISITION TIME tACQ 1.8 µs TIME BETWEEN CONVERSIONS tCYC 5 µs DATA WRITE/READ DURING CONVERSION tDATA 1.2 µs SCK Period tSCK tDSDO + 2 ns Low Time tSCKL 12 ns High Time tSCKH 12 ns Falling Edge to Data Remains Valid tHSDO 5 ns Falling Edge to Data Valid Delay tDSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 38 ns VIO Above 1.8 V 48 ns CNV Pulse Width tCNVH 10 ns Low to SDO D15 MSB Valid tEN VIO Above 3 V 21 ns VIO Above 2.7 V 27 ns VIO Above 2.3 V 35 ns VIO Above 1.8 V 45 ns High or Last SCK Falling Edge to SDO High Impedance tDIS 50 ns Low to SCK Rising Edge tCLSCK 10 ns DIN Valid Setup Time from SCK Rising Edge tSDIN 5 ns Valid Hold Time from SCK Rising Edge tHDIN 5 ns 1 See Figure 2 and Figure 3 for load conditions.
500µA IOL TO SDO 1.4V CL 50pF
002
500µA IOH
15658- Figure 2. Load Circuit for Digital Interface Timing
70% VIO 30% VIO tDELAY tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2
003
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
15658- Figure 3. Voltage Levels for Timing Rev. C | Page 7 of 10 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE