Datasheet AD7923-EP (Analog Devices) - 7

Enhanced Product AD7923-EP PIN CONFIGURATION AND FUNCTION DESCRIPTION SCLK 1 16 AGND DIN 2 15 VDRIVE CS 3 14 DOUT AGND 4 13 AD7923-EP AGND AV 5 TOP VIEW 12 DD VIN0 (Not to Scale) AV 6 11 DD VIN1 REF 7 10 IN VIN2 AGND 8 9 V
003
IN3
0- 1019 Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 SCLK Serial Clock. Logic Input. SCLK provides the serial clock for accessing data for the device. This clock input is also used as the clock source for the AD7923-EP conversion process. 2 DIN Data In. Logic Input. Data to be written to the control register is provided on this input and is clocked into the register on the falling edge of SCLK. 3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7923-EP and framing the serial data transfer. 4, 8, AGND Analog Ground. Ground reference point for all analog circuitry on the AD7923-EP. All analog input signals and any 13, 16 external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. 5, 6 AVDD Analog Power Supply Input. The AVDD range for the AD7923-EP is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range, AVDD should be from 4.75 V to 5.25 V. 7 REFIN Reference Input for the AD7923-EP. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. 12 to 9 VIN0 to VIN3 Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed into the on- chip track-and-hold. The analog input channel to be converted is selected by using the Address Bits ADD1 and ADD0 of the control register. The address bits in conjunction with the SEQ1 and SEQ0 bits allow the sequencer to be programmed. The input range for all input channels can extend from 0 V to REFIN or from 0 V to 2 × REFIN as selected via the range bit in the control register. Any unused input channels must be connected to AGND to avoid noise pickup. 14 DOUT Data Out. Logic Output. The conversion result from the AD7923-EP is provided on this output pin as a serial data stream. The AD7923-EP serial data stream consists of two leading 0s, and two address bits indicating which channel the conversion result corresponds to, followed by 12 bits of conversion data, MSB first. The output coding can be selected as straight binary or twos complement via the coding bit in the control register. The data bits are clocked out of the AD7923-EP on the SCLK falling edge. 15 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at which voltage the serial interface operates. Rev. A | Page 7 of 9 Document Outline Features Enhanced Product Features Applications General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Description Typical Performance Characteristics Outline Dimensions Ordering Guide