Datasheet AD7490-EP (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 16-Channel, 1MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP |
| 页数 / 页 | 12 / 3 — Enhanced Product. AD7490-EP. SPECIFICATIONS. Table 1. Parameter. Test … |
| 修订版 | B |
| 文件格式/大小 | PDF / 406 Kb |
| 文件语言 | 英语 |
Enhanced Product. AD7490-EP. SPECIFICATIONS. Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
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Enhanced Product AD7490-EP SPECIFICATIONS
V 1 DD = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Temperature range (EP version): −55°C to +125°C.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz Signal-to-(Noise + Distortion) (SINAD) 69 70.5 dB Signal-to-Noise Ratio (SNR) 69.5 dB Total Harmonic Distortion (THD) −84 −74 dB Peak Harmonic or Spurious Noise (SFDR) −86 −75 dB Intermodulation Distortion (IMD) fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −85 dB Third-Order Terms −85 dB Aperture Delay 10 ns Aperture Jitter 50 ps Channel-to-Channel Isolation fIN = 400 kHz −82 dB Full Power Bandwidth 3 dB 8.2 MHz 0.1 dB 1.6 MHz DC ACCURACY Resolution 12 Bits Integral Nonlinearity ±1 LSB Differential Nonlinearity Guaranteed no missed codes to 12 bits −0.95/+1.5 LSB 0 V to REFIN Input Range Straight binary output coding Offset Error ±0.6 ±8 LSB Offset Error Match ±0.5 LSB Gain Error ±2 LSB Gain Error Match ±0.6 LSB 0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos complement output coding offset Positive Gain Error ±2 LSB Positive Gain Error Match ±0.5 LSB Zero Code Error ±0.6 ±8 LSB Zero Code Error Match ±0.5 LSB Negative Gain Error ±1 LSB Negative Gain Error Match ±0.5 LSB ANALOG INPUT Input Voltage Range RANGE bit set to 1 0 REFIN V RANGE bit set to 0 0 2 × REFIN V DC Leakage Current ±1 µA Input Capacitance 20 pF REFERENCE INPUT REFIN Input Voltage ±1% specified performance 2.5 V DC Leakage Current ±1 µA REFIN Input Impedance fSAMPLE = 1 MSPS 36 kΩ LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V Input Low Voltage, VINL 0.3 × VDRIVE V Input Current, IIN VIN = 0 V or VDRIVE ±0.01 ±1 µA Input Capacitance, CIN+2 10 pF Rev. B | Page 3 of 12 Document Outline Features Enhanced Product Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide
V 1 DD = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Temperature range (EP version): −55°C to +125°C.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz Signal-to-(Noise + Distortion) (SINAD) 69 70.5 dB Signal-to-Noise Ratio (SNR) 69.5 dB Total Harmonic Distortion (THD) −84 −74 dB Peak Harmonic or Spurious Noise (SFDR) −86 −75 dB Intermodulation Distortion (IMD) fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −85 dB Third-Order Terms −85 dB Aperture Delay 10 ns Aperture Jitter 50 ps Channel-to-Channel Isolation fIN = 400 kHz −82 dB Full Power Bandwidth 3 dB 8.2 MHz 0.1 dB 1.6 MHz DC ACCURACY Resolution 12 Bits Integral Nonlinearity ±1 LSB Differential Nonlinearity Guaranteed no missed codes to 12 bits −0.95/+1.5 LSB 0 V to REFIN Input Range Straight binary output coding Offset Error ±0.6 ±8 LSB Offset Error Match ±0.5 LSB Gain Error ±2 LSB Gain Error Match ±0.6 LSB 0 V to 2 × REFIN Input Range −REFIN to +REFIN biased about REFIN with twos complement output coding offset Positive Gain Error ±2 LSB Positive Gain Error Match ±0.5 LSB Zero Code Error ±0.6 ±8 LSB Zero Code Error Match ±0.5 LSB Negative Gain Error ±1 LSB Negative Gain Error Match ±0.5 LSB ANALOG INPUT Input Voltage Range RANGE bit set to 1 0 REFIN V RANGE bit set to 0 0 2 × REFIN V DC Leakage Current ±1 µA Input Capacitance 20 pF REFERENCE INPUT REFIN Input Voltage ±1% specified performance 2.5 V DC Leakage Current ±1 µA REFIN Input Impedance fSAMPLE = 1 MSPS 36 kΩ LOGIC INPUTS Input High Voltage, VINH 0.7 × VDRIVE V Input Low Voltage, VINL 0.3 × VDRIVE V Input Current, IIN VIN = 0 V or VDRIVE ±0.01 ±1 µA Input Capacitance, CIN+2 10 pF Rev. B | Page 3 of 12 Document Outline Features Enhanced Product Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide