Errata Document AD73360 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | 6-Channel AFE Processor for General Purpose Applications Including Industrial Power Metering or Multi-Channel Analog Inputs |
| 页数 / 页 | 2 / 2 — ERRATA DOCUMENT. AD73360 Rev.1. S C L K. S D O F S. S D O. Choosing SCLK … |
| 修订版 | A |
| 文件格式/大小 | PDF / 24 Kb |
| 文件语言 | 英语 |
ERRATA DOCUMENT. AD73360 Rev.1. S C L K. S D O F S. S D O. Choosing SCLK rate and Sample Period. SCLK and Sample Rates
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ERRATA DOCUMENT AD73360 Rev.1
1 4 8 1 2 1 6
S C L K S D O F S S D O
D e vi ce 3 - C h an ne l 1 D e vice 2 - C h an ne l 1 D e D vi e ce vi ce 1 - C 1 - h C an h ne an l ne l1 1 D e vi ce 3 - C h an ne l 2 D e vice 2 - C h an ne l 2 64 S C LK s Figure 2. Cascade Timing for a Three-Device Cascade
Choosing SCLK rate and Sample Period
For a cascade of a given length, the SCLK rate and Sample Period will determine if the cascade can be used successfully. A low sample rate will allow more time for the ADC data to be read. Similarly a high SCLK rate will transmit the data in a shorter time. Since both the SCLK rate and Sample Rate are derived from the same DMCLK the number of combinations is limited. As most applications will require a predetermined sample rate, the SCLK speed will be the limitating factor in the cascade length that can be used. Table I shows the maximum cascade length for a given SCLK and Sample Rate. The table assumes that a MCLK of 16.384MHz is used.
SCLK and Sample Rates T Table I. Maximum Cascade Length with Various A SCLK (MHz) Max. Number Sample Rate ERRA of Devices (KHz)
16.384 2 64 3 32 4 16 5 8 8.192 1
DOCUMENT
64 2 32 3 16 4 8 4.096 1 32 2 16 3 8 2.048 1 16 2 8
REV.A
–2–
1 4 8 1 2 1 6
S C L K S D O F S S D O
D e vi ce 3 - C h an ne l 1 D e vice 2 - C h an ne l 1 D e D vi e ce vi ce 1 - C 1 - h C an h ne an l ne l1 1 D e vi ce 3 - C h an ne l 2 D e vice 2 - C h an ne l 2 64 S C LK s Figure 2. Cascade Timing for a Three-Device Cascade
Choosing SCLK rate and Sample Period
For a cascade of a given length, the SCLK rate and Sample Period will determine if the cascade can be used successfully. A low sample rate will allow more time for the ADC data to be read. Similarly a high SCLK rate will transmit the data in a shorter time. Since both the SCLK rate and Sample Rate are derived from the same DMCLK the number of combinations is limited. As most applications will require a predetermined sample rate, the SCLK speed will be the limitating factor in the cascade length that can be used. Table I shows the maximum cascade length for a given SCLK and Sample Rate. The table assumes that a MCLK of 16.384MHz is used.
SCLK and Sample Rates T Table I. Maximum Cascade Length with Various A SCLK (MHz) Max. Number Sample Rate ERRA of Devices (KHz)
16.384 2 64 3 32 4 16 5 8 8.192 1
DOCUMENT
64 2 32 3 16 4 8 4.096 1 32 2 16 3 8 2.048 1 16 2 8
REV.A
–2–