Datasheet ADRF6520 (Analog Devices) - 7

Data Sheet ADRF6520 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D 1 M M NBL CS VPSD CO VPS VPS CO CHP E 32 31 30 29 28 27 26 25 INP1 1 24 OPP1 INM1 2 23 OPM1 COM 3 22 COM ADRF6520 CFLT1 4 21 VGN1 TOP VIEW CFLT2 5 20 VGN2 (Not to Scale) COM 6 19 COM INM2 7 18 OPM2 INP2 8 17 OPP2 9 10 11 12 13 14 15 16 T K O M 2 MS RS CL DI VPS VPS S S CO CHP VR NOTES
002
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW IMPEDANCE GROUND PAD.
14830- Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1, 2 INP1, INM1 Channel 1 Differential Inputs, 100 Ω Differential Input Impedance. 3, 6, 19, 22 COM Analog Common. Connect COM to an external circuit common using the lowest possible impedance. 4, 5 CFLT1, CFLT2 Averaging Capacitors for RMS Detectors. The user can leave these pins open for the fastest response time and the least amount of rms averaging. 7, 8 INM2, INP2 Channel 2 Differential Inputs, 100 Ω Differential Input Impedance. 9 RST SPI Reset to Default Bit Values. This pin is active low. Pull the pin high under nonactive conditions. The transistor-transistor logic (TTL) levels are VLOW < 0.8 V and VHIGH > 2 V. 10 SCLK SPI Port Clock. The TTL levels are VLOW < 0.8 V and VHIGH > 2 V. 11 SDIO SPI Data Input and Output. The TTL levels are VLOW < 0.8 V and VHIGH > 2 V. 12, 13, 28, 29 VPS Analog Positive Supply Voltage: 3.15 V to 3.45 V. 15, 26 CHP2, CHP1 DC Offset Correction Loop Capacitors. Connect the capacitors to a circuit common. 16 VRMS RMS Detector Output. The output transfer function is 1 V/V rms × (CH1_RMS + CH2_RMS), where CH1_RMS is the differential rms voltage of the input of the Channel 1 filter, and CH2_RMS is the differential rms voltage of the input of the Channel 2 filter. The user can leave the pin open if not using the rms detector; there is no need to terminate this pin. Load this pin with at least 1 kΩ to ground; values lower than this prevent the detector output from reaching its full-scale value. 17, 18 OPP2, OPM2 Channel 2 Differential Outputs. These outputs have a 20 Ω differential output impedance. 20, 21 VGN2, VGN1 VGA2 and VGA1 Analog Gain Control. These pins operate from 0 V to 1.5 V with 30 mV/dB gain scaling. 23, 24 OPM1, OPP1 Channel 2 Differential Outputs. These outputs have a 20 Ω differential output impedance. 25 ENBL Chip Enable. Pull this pin high to enable the chip. Voltages on ENBL of less than 1.6 V disable the device. 30 COMD Digital Common. Connect this pin to an external circuit common using the lowest possible impedance. 31 VPSD Digital Positive Supply Voltage: 3.15 V to 3.45 V. 32 CS Chip Select Bar to Enable SPI Programming. CS is an SPI programming pin and is active low. The TTL levels are VLOW < 0.8 V and VHIGH > 2 V. EP Exposed Ground Pad. Connect the exposed pad to a low impedance ground pad. Rev. 0 | Page 7 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT VGAs RMS DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6520 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS SPI REGISTER AND TIMING REGISTER READ/WRITE TIMING Write Cycle Read Cycle APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING RMS DETECTOR CONNECTIONS VGA2 GAIN STEP RESPONSE LINEAR OPERATION OF THE ADRF6520 EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE